Generating method for test chip layout

Abstract

The invention relates to a generating method for a test chip layout, which comprises the following steps: firstly, selecting a target layout area; after selection, placing for one time or placing repeatedly to form a cell array; then connecting repeated units; and finally taking the connected repeated units as a test structure, placing the test structure in the addressing test chip layout and performing wiring. As the generating method generates the test structure automatically and performs wiring automatically, the design cycle of the test chip layout is greatly shortened, the error rate during designing of the test chip layout is greatly reduced, and the test accuracy is improved; and as the IP core based on the addressing methodology is adopted, the area utilization ratio of a test chip is greatly improved, and the technology test cost is greatly reduced.

Description

technical field [0001] The invention belongs to the field of chip testing, and in particular relates to a method for generating a test chip layout. Background technique [0002] With the development of microelectronics technology, integrated circuits have entered the era of ultra-deep submicron, which makes the feature size of electronic devices smaller and smaller, and the chip scale is larger and larger. Circuits with tens of millions or even more than 1 billion gates can be integrated on a single chip. The semiconductor process has been developed to 28nm, and the minimum line width corresponding to the layout is getting smaller and smaller, while the scale of the chip is getting larger and the complexity is getting higher and higher. The current mainstream lithography technology is 198nm lithography technology. In the production process of the system chip, there will be many factors that will affect the product yield. These factors include various short circuits and open...

AI Technical Summary

Problems solved by technology

Because the number of positions that need to be measured affects the yield rate is very large, the disadvantages of manually generating the test structure are: (1) There are very many positions that need to be measured in the product, even thousands, and the test pattern is generated manually It takes a lot of time; (2) Manually generating the test structure is error-prone

The shortcomings of the process of manually generating test chip templates are: (1) There are many test structures, which can be thousands to tens of thousands, and it takes a lot of time to manually place and route the test chip templates; (2) manually Placement and wiring are prone to errors; (3) The area utilization rate is very low, and the test cost is very high

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