Generating method for test chip layout

A layout and chip technology, applied in the field of test chip layout generation, can solve the problems of error-prone test structure, low area utilization rate, high test cost, etc., and achieve the goal of reducing process test cost, improving test accuracy, and improving area utilization rate Effect

Inactive Publication Date: 2013-06-12
SEMITRONIX
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AI Technical Summary

Problems solved by technology

Because the number of positions that need to be measured affects the yield rate is very large, the disadvantages of manually generating the test structure are: (1) There are very many positions that need to be measured in the product, even thousands, and the test pattern is generated manually It takes a lot of time; (2) Manually generating the test structure is error-pr

Method used

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  • Generating method for test chip layout
  • Generating method for test chip layout
  • Generating method for test chip layout

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Example Embodiment

[0061] The present invention will be further described below in conjunction with the drawings and specific embodiments, but the protection scope of the present invention is not limited to this.

[0062] Such as figure 1 As shown, a method for generating the layout of a test chip is to first select the area of ​​the chip to be tested, and then place it once or repeatedly to form a unit array, then connect the repeated units, and finally use the repeatedly connected unit as the test The structure is placed in the addressable test chip layout and wired. Specifically include the following steps:

[0063] (1) Generate test structure:

[0064] 1.1. Select a layout area that contains the required test location in the chip layout; image 3 In the middle, the left side is the chip layout, the middle is the selected layout area, and the right is the partial enlargement containing the required test location. Figure 4 In the middle, the left is the chip layout, and the middle is the selected ...

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Abstract

The invention relates to a generating method for a test chip layout, which comprises the following steps: firstly, selecting a target layout area; after selection, placing for one time or placing repeatedly to form a cell array; then connecting repeated units; and finally taking the connected repeated units as a test structure, placing the test structure in the addressing test chip layout and performing wiring. As the generating method generates the test structure automatically and performs wiring automatically, the design cycle of the test chip layout is greatly shortened, the error rate during designing of the test chip layout is greatly reduced, and the test accuracy is improved; and as the IP core based on the addressing methodology is adopted, the area utilization ratio of a test chip is greatly improved, and the technology test cost is greatly reduced.

Description

technical field [0001] The invention belongs to the field of chip testing, and in particular relates to a method for generating a test chip layout. Background technique [0002] With the development of microelectronics technology, integrated circuits have entered the era of ultra-deep submicron, which makes the feature size of electronic devices smaller and smaller, and the chip scale is larger and larger. Circuits with tens of millions or even more than 1 billion gates can be integrated on a single chip. The semiconductor process has been developed to 28nm, and the minimum line width corresponding to the layout is getting smaller and smaller, while the scale of the chip is getting larger and the complexity is getting higher and higher. The current mainstream lithography technology is 198nm lithography technology. In the production process of the system chip, there will be many factors that will affect the product yield. These factors include various short circuits and open...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 刘得金郑勇军欧阳旭潘伟伟
Owner SEMITRONIX
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