An esd protection circuit

Abstract

The invention relates to an electro-static discharge (ESD) protective circuit. The ESD protective circuit is in a diode series structure which is capable of restraining a Darlington effect. According to the ESD protective circuit, two ends of a P substrate are respectively provided with two N traps, wherein the bottoms of each two traps are connected into a whole. A P base region is arranged between each two N traps. Each N trap of four N traps is provided with an N+ diffusion active region. Each P base region is provided with a P+ diffusion active region and an N+ diffusion active region. Four of N+ diffusion active regions are connected through wires, and then are connected with power source potential voltage drain drain (VDD). A first P+ diffusion active region is connected with an electricity positive electrode. A fifth N+ diffusion active region is connected with a second P+ diffusion active region through wires. A sixth N+ diffusion active region is connected with an electricity negative electrode. The ESD protective circuit has the advantages of greatly reducing currents flowing to the P substrate, and being capable of effectively restraining the Darlington effect, good in clamping capacity, small in leakage current, good in ESD resistant capacity of unit area, and capable of effectively restraining occurrence of a latch-up effect.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits and relates to an improved structure of cascaded diodes used for electrostatic discharge protection of radio frequency circuits, in particular to an ESD protection circuit. Background technique [0002] For integrated circuits, the electrostatic discharge (ESD) process usually only refers to the electrostatic discharge process with a duration of about 150ns caused by an external object touching a certain connection point of the chip. This process will generate very high transient current and transient Voltage (current of tens of amperes or voltage of thousands of volts), the high electric field caused by ESD will break down the gate oxide layer of the input stage in the integrated circuit, which may cause the integrated circuit chip to fail. As the size of MOS transistors in integrated circuits is getting smaller and smaller, the thickness of the gate oxide layer is also getting thinne...

AI Technical Summary

Problems solved by technology

The gate-grounded NMOS transistor is the most commonly used electrostatic protection circuit, but its anti-ESD ability per unit area is poor, and the layout area required to obtain high ESD protection ability is too large; the CDS transistor has a simple structure, strong clamping ability, and small parasitic capacitance. However, the Darlington effect will appear in the CMOS process, which will affect its discharge capability; the SCR tube has strong ESD resistance per unit area and low leakage current, but its unique snapback characteristics are likely to cause latch-up

[0004] like figure 1 Shown is a traditional cascaded diode, with 2 N wells on a P substrate, each with a P+ diffused active area and an N+ diffused active area, the cascaded diode closest to the edge The P+ diffused active area is connected to the electrical anode, and the N+ diffused active area closest to the edge is connected to the electrical cathode. However, in the CMOS process, the diode is actually realized by the BE junction of the vertical PNP tube, so the CDS tube becomes It has become a PNP tube with a special connection method: the base of the PNP tube of the previous stage is connected to the emitter stage of the subsequent stage, and the collectors of all the PNP tubes are connected in common and connected to the ground (GND). As the number increases, the collector currents of all PNP transistors also increase, and the trigger voltage of CDS transistors also decreases, which is called the Darlington effect, which limits its application range

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