Inverted order arrangement system and method for fast Fourier transformation/discrete Fourier transformation (FFT/DFT) and operating system for FFT/DFT

Abstract

The invention relates to the field of communication, in particular to an inverted order arrangement system and an inverted order arrangement method for fast Fourier transformation / discrete Fourier transformation (FFT / DFT) and an operating system for FFT / DFT. The inverted order arrangement system comprises a signal control device and an order inverting device, wherein the signal control device is used for acquiring a control signal corresponding to data to be subjected to order inversion at each point and sending the control signal to the order inverting device to make the order inverting device invert the order of the data at each point according to the received control signal; and the order inverting device is used for inverting the order of the data to be subjected to order conversion according to the received control signal. The system solves the problems that the inverted order arrangement time for FFT / DFT is too long and the utilization efficiency of a vector processor is low when the vector processor is used for computing FFT / DFT, and the vector computing efficiency for FFT / DFT can be improved.

Description

Technical field [0001] The present invention relates to the technology of the communication field, in particular to an FFT / DFT reverse order arrangement system and method and an operation system thereof. Background technique [0002] Fast Fourier Transformation (FFT) and Discrete Fourier Transformation DFT are widely used in signal processing and communication systems, especially LTE (Long Term Evolution) involving Orthogonal Frequency Division Multiplexing (OFDM) , Long Term Evolution), Digital Audio Broadcast (DAB) and other communication systems. Traditional FFT / DFT algorithms, whether it is time decimation (DIT) or frequency decimation (DIF) algorithms, need to perform a special reverse order operation on input or output data, and whether it is DIT algorithm or DIF algorithm, in the vector processor It is necessary to introduce a certain cross-connection in the vector processing unit during implementation, otherwise the efficiency of the vector processor will not be fully ut...

AI Technical Summary

Problems solved by technology

The traditional FFT / DFT algorithm, whether it is time extraction (DIT) or frequency extraction (DIF) algorithm, requires a special reverse operation on the input or output data, and whether it is DIT algorithm or DIF algorithm, in the vector processor It is necessary to introduce a certain cross-connection in the vector processing unit during implementation, otherwise the efficiency of the vector processor cannot be fully utilized, resulting in an increase in power consumption

[0003] like figure 1 As shown, it is the flow chart of the FFT time extraction algorithm for 16-point positive sequence input. If it is directly implemented in the vector processor of 4 DIT butterflies, the highest efficiency is that each level of FFT is completed with two vector butterfly operations, from figure 2 It can be seen that the last two stages of FFT need to introduce cross-connects to make full use of all 4 butterflies, otherwise the efficiency of the vector processor cannot be fully utilized, especially the last stage can only calculate one butterfly at a time, resulting in a great reduction in efficiency , increasing power dissipation

On the other hand, although the introduction of cross-connection can improve the efficiency of calculation, the number of connection is huge when there are many calculation units. For example, when the vector calculation unit has 16 DIT units, then the FFT operation needs to be introduced in the last four stages. Cross-connection, and the total number of cross-connection is as high as 4000 (if the data bit width is 16), a large number of cross-connection leads to an increase in charging and discharging current and power consumption

[0004] In addition, in addition to the above-mentioned cross-connection problem, the standard FFT / DFT algorithm requires a special data reverse operation in addition to the butterfly operation

The reverse order of data can be carried out in serial or parallel mode. In serial mode, software or hardware can be used to calculate the address of each data after reverse order. This method consumes a lot of time for reverse order. When there are many vector butterfly units, the reverse order time may be is several times the time consumed by the butterfly operation, resulting in inefficient vector processors

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