Method for forming shallow groove isolation area

A shallow trench isolation area and trench technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems affecting the height of isolation structures

Inactive Publication Date: 2013-07-03
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The process based on the above process has the following two problems, which affect the height of the isolation structure (Step height) between the regions:

Method used

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  • Method for forming shallow groove isolation area
  • Method for forming shallow groove isolation area
  • Method for forming shallow groove isolation area

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Embodiment Construction

[0042] The present invention divides the planarization of chemical mechanical polishing into two steps by arranging two separated chemical mechanical polishing stop layers, which not only satisfies the requirement that the width of the chemical mechanical polishing is so large that depressions will be generated in the chemical mechanical polishing The recess depth of the insulating oxide layer in the trench is reduced. More importantly, this method can also easily adjust the height of the shallow trench isolation structure in the narrower trench by controlling the process parameters. effect, and enables particularly narrow trenches in which the insulating oxide layer is filled by two depositions in narrower trenches and shallow trenches in relatively wide trenches in which the insulating oxide layer is filled by three depositions The height of the groove isolation structure is consistent.

[0043] In specific implementation, its specific steps may include:

[0044] Provide a ...

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Abstract

A method for forming a shallow groove isolation area comprises the steps of providing a semiconductor substrate comprising a wide line area and a thick line area; sequentially forming a pad oxide layer, a first grinding stopping layer, an etching stopping layer and a second grinding stopping layer on the semiconductor substrate; etching the pad oxide layer, the first grinding stopping layer, the etching stopping layer, the second grinding stopping layer and the semiconductor substrate to form grooves; forming an insulation oxide layer which at least enables the groove to be fully filled; conducting first grinding on the insulation oxide layer until the second grinding stopping layer exposes; removing the second grinding stopping layer; conducting second grinding on the insulation oxide layer until the first grinding stopping layer exposes; removing the first grinding stopping layer; and removing the pad oxide layer. The method can be used for well controlling the height of an isolation structure of a shallow groove and enables the heights of all isolation structures of the shallow grooves to be same.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation region. Background technique [0002] As the integration level of semiconductor devices continues to increase, isolation techniques for electrically isolating adjacent devices become more and more important. The shallow trench isolation process is an isolation technology widely used in the manufacture of highly integrated semiconductor devices. [0003] The shallow trench isolation process realizes effective isolation of the active region by forming an isolation trench defining an active region on a semiconductor substrate and filling the isolation trench with an insulating material. Usually, some areas in semiconductor devices have higher active area density, and the trench width for active area isolation is smaller (<0.2 μm). This area is called "dense line area"; The area density is low, and the trench width for is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
Inventor 邵群
Owner SEMICON MFG INT (SHANGHAI) CORP
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