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A data cache device applied to parallel filtering operation

A data buffering and data technology, which is applied in electrical digital data processing, computing, memory systems, etc., can solve the problems of inappropriate parallel filtering operations and insufficient computing efficiency of data buffering devices, and achieve the effect of maximum utilization and reduction of memory access times.

Active Publication Date: 2015-12-23
BEIJING SMART LOGIC TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The technical problem to be solved by the present invention is that the existing data buffering device is not suitable for parallel filtering operation, resulting in insufficient operation efficiency

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  • A data cache device applied to parallel filtering operation
  • A data cache device applied to parallel filtering operation
  • A data cache device applied to parallel filtering operation

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Embodiment Construction

[0033] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] The present invention needs to utilize a memory (or multi-granularity memory) that supports multi-granularity parallel reading and writing. For the description of the multi-granularity memory, refer to the Chinese patent publication titled "Multi-granularity Parallel Storage System and Memory" with application number 201110460585.1.

[0035] figure 1 It shows the position of the data buffer device for parallel filtering operation in the two-dimensional filtering device of the present invention. Such as figure 1 As shown, the figure is a structure diagram of the device corresponding to the parallel filtering operation. The device mainly includes the following parts: multi-granularity memory 10 , data cache device ...

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Abstract

The invention discloses a data caching device applied to parallel filtering operation. The data caching device applied to the parallel filtering operation comprises a caching area entity, reading caching logic, initializing caching logic and updating caching logic, wherein the caching area entity is used for caching data from a multi-granularity memorizer, the reading caching logic is used for receiving reading caching area enable signals, reading caching area column numbers and reading caching area in-column excursion and reading a certain list of data of the caching area entity according to the signals, the initializing caching logic is used for initializing the caching area entity when initialization starting signals are valid, and the updating caching logic is used for bodily moving the caching area entity according to lists when list movement signals are valid and meanwhile outputting signal groups of the multi-granularity memorizer. According to the data caching device applied to the parallel filtering operation, data can be processed before filtration, data needed by the parallel filtering operation are provided in the filtration, a data locality theory is fully utilized, the number of visiting times and the number of storing times are reduced, and the maximum utilization rate of the data is achieved.

Description

technical field [0001] The invention relates to the technical field of digital signal processors and microprocessors, in particular to a data buffer structure for filtering operations, which is closely related to filtering algorithms and integrated circuit structures. Background technique [0002] In signal processing systems such as image processing, image filtering is an indispensable processing operation for obtaining images with a low signal-to-noise ratio. For different filtering templates, the calculation amount of two-dimensional filtering is different. Generally, for a K×K filtering template, calculating each filtering result requires K 2 multiplications and K 2 addition, then for an input matrix of size M×N, the amount of computation required is 2MNK 2 , so two-dimensional filtering is a computationally intensive algorithm. [0003] For the huge amount of calculation above, its data use has great local characteristics. For a K×K filter template, two adjacent filt...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F12/0804G06F12/0811
Inventor 王东琳尹磊祖杨勇勇谢少林汪涛
Owner BEIJING SMART LOGIC TECH CO LTD