30results about How to "Reduce processing failure" patented technology

In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure.

In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.

A closed chemical introduction system used to deliver active ingredients in liquid chemical to a chemical vapor deposition system includes a robust, moisture-free cartridge containing a defined dose of liquid chemical. The cartridge is placed on a mounting slot specially configured to receive the cartridge. Upon initiating the system, a first linear mechanical actuator securely holds the cartridge in the slot, while an extraction lance attached to a second linear mechanical actuator punctures the cartridge from the bottom, extracts the liquid chemical and delivers it to a vaporization chamber. The vaporization chamber evaporates the liquid chemical and delivers the vapors containing the active ingredients to the chemical vapor deposition system. The chemical vapor deposition system may include a treatment chamber, a conveyor, a compressed clean air system to provide separate treatment compartments within the chamber, a moisture system, a chemical vapor system, and a neutralization system to neutralize harmful byproducts.

A thin film transistor array panel is provided according to one or more embodiments. In an embodiment, the thin film transistor array panel includes: a base substrate that has a display area and a peripheral area; a plurality of thin film transistors that are formed in the display area; a plurality of signal input pads that are formed in the peripheral area and that are formed long in a first direction; and a plurality of signal lines that are connected to the thin film transistors and the signal input pads, wherein at least a part of each of the plurality of signal input pads is arranged in a line along the first direction.

The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

An operational control method is provided for a machine tool that includes a plurality of tool holders with a cutting-tool. The machine tool relatively moves the tool holders with respect to a workpiece to process the workpiece. The operational control method includes determining whether an abnormality has occurred in the cutting-tool during a processing or not, determining whether a simultaneous processing in which at least two or more of the tool holders perform the processings to an identical workpiece is being performed or not and whether the cutting-tool having the detected abnormality is the cutting-tool that is performing the simultaneous processing or not when the abnormality is detected, and causing the tool holder with the cutting-tool having the detected abnormality to take an abnormality avoidance operation and another of the tool holders to take a response operation based on a determination result at the determining of the simultaneous processing.

The invention discloses a method for machining spatial holes by using a large ellipsoid on a numerical control boring-milling machine. The method comprises the following steps of: determining the range and the clamping datum of a machined hole by applying a software analysis workpiece; compiling a numerical control machining program of the spatial hole; checking the numerical control machining program by applying simulation software; clamping and correcting according to a numerical control requirement and machining the spatial hole with an allowance; detecting the spatial position precision of the machined hole, adjusting the numerical control machining program according to a detection result and then machining the spatial hole to a required precision; and repeatedly clamping and machining a spatial hole in another range until holes on the workpiece are all machined. The invention has the advantages that multiple groups of spatial holes on the large ellipsoid can be machined by using a numerical control boring-milling machine, thereby meeting the requirement on the position precision; the maximum utilization ratio of a process is realized without being limited by the system of thenumerical control boring-milling machine, and the compiling of the machining program can be finished only by updating part models and mathematical parameters; and the process is safe and reliable andhas high efficiency.