Vertical-type semiconductor device

Abstract

In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

Description

RELATED APPLICATION[0001]This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2008-0052368, filed on Jun. 4, 2008 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.BACKGROUND[0002]1. Field[0003]Example embodiments relate to a vertical-type semiconductor device, a method of manufacturing the vertical-type semiconductor device and a method of operating the vertical-type semiconductor device. More particularly, example embodiments relate to a semiconductor device having a vertical-type pillar transistor suitable for a cell array structure, a method of manufacturing the semiconductor device and a method of operating the semiconductor device.[0004]2. Description of the Related Art[0005]Generally, as semiconductor devices become highly integrated, dimensions of active regions are reduced, and channel lengths of MOS transistors formed in the active regions are reduced. As the...

AI Technical Summary

Benefits of technology

The patent text describes a vertical-type semiconductor device with high performance. The device includes a single-crystalline semiconductor pattern with a pillar shape on a substrate, a gate with a linear shape surrounding the semiconductor pattern, and a mask pattern on the upper sidewalls of the gate. The device also includes a first impurity region in the substrate under the semiconductor pattern and a second impurity region under the upper surface of the semiconductor pattern. The device can be manufactured using a method that includes forming a spacer on the sidewalls of the gate and the mask pattern. The patent text also describes a data storage structure, such as a capacitor, a magnetoresistive tunnel junction structure, or a phase changeable structure, that can be provided on the contact plug of the device. The technical effects of the patent text include improved performance and reliability of the vertical-type semiconductor device.

Problems solved by technology

Accordingly, it becomes difficult to control the MOS transistor by a gate.

That is, when the semiconductor pattern has any crystal defect, leakage current properties and threshold voltages in the vertical-type pillar transistor formed in each of the semiconductor patterns may not be uniform.

However, because it is considerably more difficult than the bulk substrate to form the semiconductor pattern without any crystal defect, it may be not easy to ensure electrical properties of the vertical-type pillar transistors.

Additionally, processes of forming a gate and a source / drain in the pillar-shaped semiconductor pattern are considerably more complicated than those in the substrate.

Further, when the vertical-type pillar transistors are formed to have an array structure, more complicated processes need to be additionally performed, such that the incidence of process failures increases.

Accordingly, it may be difficult to manufacture a memory device of an array structure including the vertical-type pillar transistors.

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