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Thread-aware multi-core data prefetching self-regulation method

A data prefetching and threading technology, applied in the field of performance optimization of multi-core storage systems, can solve problems such as affecting cache hits, and achieve the effect of improving hit rate and reducing competition.

Active Publication Date: 2013-08-07
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since prefetching will lead to cache replacement, each thread's prefetch request may affect other thread's private cache (cache) hits

Method used

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  • Thread-aware multi-core data prefetching self-regulation method
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  • Thread-aware multi-core data prefetching self-regulation method

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0021] Embodiment 1, figure 1 and figure 2 Combined with a thread-aware multi-core data prefetch self-adjustment method; including a multi-core thread-aware multi-core data prefetch device; such as figure 1 As shown, the multi-core thread-aware multi-core data prefetching device includes multiple (at least two) processors 101 and routers 103; the processors 101 and the processors 101 are connected through an on-chip interconnection network.

[0022] Such as figure 2 As shown, each processor 101 includes a number of nodes 131 (ie Tile), a number of L1 caches (ie figure 1 in the L1 data cache 102) and a L2 cache (i.e. figure 1 Shared L2 cache 105 in ), each node 131 has a one-to-one correspondence with each L1 cache, that is, each node 131 independently owns a private L1 data cache 102; all nodes 131 Both share the L2 cache (that is, share the L2 cache 105, which is assumed to be the last cache LLC on the chip), several nodes 131 (Tile), several L1 caches and a L2 cache ar...

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Abstract

The invention discloses a thread-aware multi-core data prefetching self-regulation method. The method comprises a first step of performing dynamical feedback information statistics: calculating storage access behaviors and prefetching behavior information of every thread through a hardware counter; a second step of performing index calculation: calculating memory access characteristics for measuring competition degree of every thread and prefetching characteristic indexes according to results of the dynamical feedback information statistics; a third step of performing thread classification: classifying the threads according to the memory access characteristics and the prefetching characteristic indexes of every thread; a fourth step of performing prefetching adjustment: adjusting a prefetching mode and radical degree according to thread classification results; a fifth step of performing attacking prefetching filtering: filtering prefetching requests which may cause invalidity of shared data.

Description

technical field [0001] The invention relates to the field of performance optimization of a multi-core storage system, in particular to a thread-aware multi-core data prefetch self-adjustment method. Background technique [0002] Storage access latency has become one of the key bottlenecks for processor performance improvement. In order to reduce the performance loss caused by storage access delay, researchers proposed a hardware data prefetch mechanism. Prefetching refers to fetching instructions or data from off-chip memory to cache (cache) or prefetch buffer before the processor accesses them. The analysis of a large number of application characteristics shows that the access patterns of instructions and data have strong regularity under certain circumstances, which makes it possible to predict the access address in advance and retrieve the corresponding data. Data prefetching technology has been proven to effectively improve performance on traditional single-core proces...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F12/0862
Inventor 刘鹏辛愿刘勇于绩洋黄巍
Owner ZHEJIANG UNIV
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