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Multiply add accumulator

A multiplier-adder and multiplier technology, which is applied in the field of multiplier-adder with bit width configuration resources, can solve problems affecting performance, etc., and achieve the effect of improving computing speed, improving resource utilization, and high resource utilization

Active Publication Date: 2013-08-21
CAPITAL MICROELECTRONICS
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Problems solved by technology

This greatly affects the performance in the case of small bit width output

Method used

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Embodiment Construction

[0021] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0022] The multiplier-adder (MAC IP) of the present invention can realize a first digit threshold (first digit), such as 18*18bit (including Below) with 40bit accumulation operation, can also realize 2 parallel second digit thresholds (second digit), such as 9*9bit (including below) and with 20bit accumulation operation, support signed or unsigned number.

[0023] In MAC IP, in order to save the area and improve the operation speed, the Modified Radix-4booth Multipliers algorithm is adopted. At the same time, when the partial product (Partial Product) is accumulated, the compression technique in the algorithm is fully utilized, and the compression task is assigned to two compressors. The parallel implementation of the processor improves the operation speed. In addition, on the same IP resource, one 18*18bit or two 9*...

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Abstract

The invention relates to a multiply add accumulator which comprises more than one auxiliary multiply add accumulators. The multiply add accumulator comprises two auxiliary multiply add accumulators, wherein each auxiliary multiply add accumulator particularly comprises a partial product generator, a partial product compressor and an accumulation compressor. The partial product generator is used for multiplying a multiplier smaller than a first-digit threshold value by a multiplicand smaller than the first-digit threshold value to obtain partial product data; the partial product compressor is used for compressing the partial product data to obtain partial product compression data; and the accumulation compressor is used for compressing data of partial products and accumulating addition data to obtain summation data. The multiply add accumulator can achieve one 18*18 bit or two parallel 9*9 bit multiplication, addition and accumulation operation, is high in resource utilization rate, improves the arithmetic speed in operating large bit-width data and improves resource utilization rate when operating small bit-width data.

Description

technical field [0001] The invention relates to a multiplier-adder, in particular to a multiplier-adder which can configure resources according to the bit width of an operand. Background technique [0002] With the improvement of FPGA chip capacity and the development of technology, many FPGAs are pre-designed and embedded with hardware multiplier-adder (MAC IP). If the user needs to implement multi-bit binary multiplication, addition or accumulation operations, in order to avoid occupying a large number of configurable logic and routing resources (PLB), it is often implemented by calling this hardware multiplier module (MAC IP). For example, if four 8*8bit multiplication and accumulation operations need to be implemented in parallel, the user can instantiate four MAC IP implementations in the code. This method is very good. Users don't have to worry about whether the MAC IP implementation is accurate, and it also saves a lot of configurable resources. However, when the ex...

Claims

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Application Information

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IPC IPC(8): G06F7/57
Inventor 王军宁邹丽娜朱建彰王强
Owner CAPITAL MICROELECTRONICS
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