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CIS wafer integration testing machine

A technology of wafer and height adjustment mechanism, applied in testing optical performance, single semiconductor device testing, etc., can solve the problems of inconvenient operation, can not meet the needs of CIS chip wafer-level testing, etc., to achieve convenient operation, compact structure, replacement Convenient and fast effect

Active Publication Date: 2013-08-28
JIAXING JINGYAN INTELLIGENT EQUIP TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The existing CIS wafer-level testing machine has a simple structure and inconvenient operation, and an auxiliary light source needs to be added during the test, which cannot meet the requirements for wafer-level testing of CIS chips.

Method used

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  • CIS wafer integration testing machine

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Experimental program
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Embodiment Construction

[0027] The specific implementation of the CIS wafer forming and testing machine of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0028] See attached figure 1 , 2 , 3. The CIS wafer tester includes a base 1 and a light source device 2, the light source device 2 is set on the base 1 through two sets of sliding platforms 3 and 4 whose displacement directions are perpendicular to each other. The light source device 2 comprises a lens mounting plate 5, the lens mounting plate 5 is arranged on the top of the light source device, and a plurality of lens mounting holes 6 are arranged on the lens mounting plate 5, and the lens mounting holes 6 are arranged in a dot matrix, and the distance between them is the same as that to be measured. The distance between the chips on the CIS wafer is corresponding or multiplied. A lens is arranged in each mirror delivery mounting hole 6 . A light source mounting plate 7 is arranged below...

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Abstract

The invention relates to the technical field of the integrated circuit chip processing technology, and discloses a CIS wafer integration testing machine. The CIS wafer integration testing machine comprises a base and a light source device, wherein the light source device is arranged on the base, the light source device comprises a lens installation plate, a plurality of lens installation holes are formed in the lens installation plate, a lens is arranged in each lens installation hole, a light source installation plate is arranged below the lens installation plate, a plurality of light source plates are arranged in the light source installation plate, and the plurality of light source plates correspond to the plurality of lens installation holes one to one. Due to the fact that a sliding platform is arranged, the lenses are made to be accurately aligned with the chips, due to the fact that light sources are arranged, the integration testing machine is compact in structure and convenient to operate, and due to the installation method of the lenses and the light sources, the lenses and the light sources can be conveniently and rapidly replaced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit chip processing, in particular to a CIS wafer forming and testing machine. Background technique [0002] CIS chip is an image signal processor chip, which is specially designed for image sensor chip, it processes the received light (image), and is widely used in scanners, fax machines, digital video cameras, and cameras. The CIS wafer-level tester takes the whole packaged wafer as the test object, and tests the electrical performance and image performance of each CIS chip on the wafer according to the method of the mid-test probe station. The chip test processor installed in JEDEC or CHIP tray has the advantages of simplicity, convenient use, low cost, and not easy to cause damage to the chip. [0003] The existing CIS wafer-level testing machine has a simple structure and inconvenient operation, and an auxiliary light source needs to be added during the test, which cannot meet the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26G01M11/02
Inventor 朱玉萍岑刚
Owner JIAXING JINGYAN INTELLIGENT EQUIP TECH