Accelerating core virtual scratch pad memory method based on heterogeneous multi-core platform
A heterogeneous multi-core and memory technology, applied in the field of heterogeneous multi-core platform memory access optimization, can solve problems affecting the performance of heterogeneous multi-core platforms, limited data bus bandwidth, slow access speed, etc., to save SPM size and improve interaction speed , the effect of reducing costs
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Example Embodiment
[0021] The present invention will be further described below with reference to the drawings and specific embodiments.
[0022] Such as figure 1 As shown in the storage hierarchy diagram of the heterogeneous multi-core platform, L1 Cache is the first level cache of general processing cores, which is private to each general processing core; L2 Cache is the second level cache, shared by all general processing cores, but Due to the fact that the memory access feature of the accelerated core is very different from that of the general-purpose processing core, it does not participate in the shared L2 Cache; SPM is the abbreviation of Scratch Pad Memory, and SPM is used as the local memory of the accelerated core to store the processing of the accelerated core. The generated local data and act as a cache between the acceleration core and the memory.
[0023] Such as figure 2 As shown, the present invention is figure 1 On the basis of the storage hierarchy in, make some optimization chan...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap