3d transmission lines for semiconductors

Abstract

A transmission line structure of a semiconductor RF or wireless loop and a method for forming the same are provided. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground layer; and a second die including a second substrate, a second Insulation and signal transmission lines. The second die may be positioned over and spaced from the first die. The underfill is disposed between the ground layer of the first die and the signal transmission line of the second die. In summary, the ground plane of the first die and the transmission line of the second die together with the underfill form a compact transmission line structure. In some embodiments, transmission line structures may be used in microwave applications. The invention also provides a semiconductor 3D transmission line.

Description

technical field [0001] The present invention relates generally to the field of semiconductor structures, and more particularly, to conductive transmission lines of semiconductor structures and methods of forming the same. Background technique [0002] Semiconductor packages equipped with wireless data and communication systems contain various RF (radio frequency) transmission structures, sometimes built on the chip or within the package. The frequency of RF signals is generally considered to be in the range of about 3 kHz to 300 GHz, while the frequency domain between 300 MHz (0.3 GHZ) and 300 GHz is generally referred to as microwaves. Electromagnetic RF waves or signals are transmitted through a semiconductor package or device using conductive structures called "transmission lines." As examples, transmission lines are used to interconnect individual electronic components together in Monolithic Microwave Integrated Circuits (MMICs) and for interconnecting MMICs together wi...

AI Technical Summary

Problems solved by technology

[0004] With the continuous advancement of semiconductor technology and the reduction of chip package size (such as by adopting 3D die stacking), the distance between the metal layers of conductive CMOS (complementary metal oxide semiconductor) structures becomes smaller and smaller, resulting in metal layer The capacitance between the growing, which impairs the performance of the RF device

Furthermore, as die packages shrink at advanced semiconductor manufacturing technology nodes such as 20nm processes, it becomes increasingly difficult to design and fabricate on-chip transmission line structures within a single chip or die

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