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Package structure

A technology of packaging structure and chip structure, which is applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., and can solve problems such as electromagnetic interference

Active Publication Date: 2016-12-14
NAN YA TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The invention provides a packaging structure to solve the defect of electromagnetic interference between different packaging structures

Method used

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Embodiment Construction

[0026] Although the present invention is disclosed as follows with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is defined by the claims. In order not to obscure the spirit of the present invention, details of some known structures and process steps will not be disclosed here.

[0027] Likewise, the accompanying drawings represent schematic diagrams of devices in preferred embodiments, but are not intended to limit the size of the devices. In particular, to make the present invention more clearly presented, the sizes of some components may be enlarged in the drawings. Moreover, the same components disclosed in multiple preferred embodiments will be marked with the same or similar symbols to make the description easier and clearer.

[0028] refer to figur...

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Abstract

The invention discloses a packaging structure, comprising a carrier board; at least one chip structure arranged on the carrier board; a packaging material layer covering and directly contacting the chip structure; and a plurality of filler particles evenly distributed in the packaging In the material layer, each filler particle includes a dielectric core, an insulating layer, the insulating layer covers the dielectric core, and a conductive layer, which is arranged between the dielectric core and the insulating layer and covers the dielectric core in the forward direction.

Description

technical field [0001] The invention relates to a packaging structure, in particular to a packaging structure used for chip packaging. Background technique [0002] As we all know, packaging technology is actually to isolate the chip from the outside world to protect the chip circuit and avoid electrical performance degradation. On the other hand, the packaged chip is also easier to install and transport. The quality of the packaging technology also directly affects the performance of the chip itself The play and the design and manufacture of the PCB (printed circuit board) connected to it, so it is crucial. [0003] With the development of memory, the existing two-dimensional packaging technology is gradually replaced by three-dimensional packaging technology. The advantage of three-dimensional packaging is that it can increase the density of interconnect lines and reduce the package size (form factor). In the three-dimensional packaging of chip stacking, the chips are bon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/552
CPCH01L2924/15311H01L2224/32145H01L2224/32225H01L2224/48227H01L2224/73265H01L2924/00
Inventor 陈逸男徐文吉叶绍文刘献文
Owner NAN YA TECH
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