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The method of using space redundancy to reduce the times of erasing and writing eeprom pages during transaction processing

A transaction processing and space redundancy technology, which is applied in the direction of memory address/allocation/relocation, etc., to achieve the effect of overcoming running speed and improving transaction processing efficiency

Active Publication Date: 2016-12-14
SHANGHAI FUDAN MICROELECTRONICS GROUP
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0010] Moreover, this method requires additional RAM cache, which is only suitable for small environments with relatively fixed application scenarios. Otherwise, the size of the RAM cache and the cache search process of any read operation will be challenged.

Method used

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  • The method of using space redundancy to reduce the times of erasing and writing eeprom pages during transaction processing
  • The method of using space redundancy to reduce the times of erasing and writing eeprom pages during transaction processing
  • The method of using space redundancy to reduce the times of erasing and writing eeprom pages during transaction processing

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Embodiment Construction

[0046] based on the following Figure 1 to Figure 6 , specifically explain the preferred embodiment of the present invention.

[0047] like figure 1 Shown, the present invention provides a kind of method utilizing space redundancy to reduce the number of erasing and writing times to EEPROM page in transaction process, comprises the following steps:

[0048] Step 1. Make each page in the space that needs to be protected by the transaction processing mechanism in the EEPROM physically correspond to two pages (PA and PB), one of which is used as the current page, and the other page is used as the shadow page;

[0049] Step 2, open up page state area TR_RAM in RAM, open up current page state area TR_EEPROM and page state shadow area TR_EEPROM_SHADOW in EEPROM respectively, be used to store page state information;

[0050] Use 2 bits to map the page status of EEPROM;

[0051] The status of each page is marked by two bits in the corresponding page status area TR_RAM, the "high bi...

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Abstract

The invention discloses a method for reducing erasing frequency of an EEPROM (electrically erasable programmable read-only memory) page during transaction processing by spatial redundancy. The method includes that each page in an EEPROM space protected by transactions physically corresponds to a shadow page; during data writing, data are written into the shadow page according to page state information in an RAM (random access memory) and a status bit is set; during data reading, data are returned according to the page state information in the RAM; during submitting of transaction data, only through an operation on the status bit and judgment of a CRC (cyclic redundancy check), the shadow page is promoted as a current page in position, and a previous current page is demoted as a shadow page; during discarding of transaction processing data, finding the previous current page according to the status bit stored by an EEPROM. Unnecessary EEPROM writing frequency is reduced during transaction processing, and influences on operation speed and EEPROM service life due to frequent modification of the EEPROM during transaction processing are eliminated, so that transaction processing efficiency is improved.

Description

technical field [0001] The invention relates to an embedded system, in particular to a method for reducing the erasing and writing times of EEPROM (electrically erasable read-only memory) pages during transaction processing by using space redundancy. Background technique [0002] When an interruption occurs during the operation of sensitive information such as transaction amount and password, the key is how to ensure the integrity of the transaction processing mechanism, that is, the transaction is either updated successfully or maintains the original value. Therefore, for devices requiring high security, especially smart cards, perfect transaction processing is particularly important. [0003] Traditional transaction processing methods are generally divided into two types, the method of saving old data and the method of saving new data: A. Save old data method: [0004] Save the old value of the target address in the transaction processing area, set the data valid flag in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02
Inventor 邬佳希王元彪陈安新李清张纲谢懿
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP
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