Method for testing and scheduling hard-core-based three-dimensional SoC (system on chip) under constraint of power consumption

Abstract

The invention relates to a method for testing and scheduling a hard-core-based three-dimensional SoC under the constraint of power consumption, belongs to the technical field of three-dimensional SoC testing and scheduling, and solves the problem that the testing time of the three-dimensional SoC cannot be optimized under the condition that the three-dimensional SoC simultaneously comprises coarse-grained IP cores and fine-grained IP cores. The method specifically comprises the process as follows: the hard-core-based three-dimensional SoC comprises the coarse-grained IP cores and the fine-grained IP cores; a three-dimensional SoC testing and scheduling mathematical model is established, and xij represents a binary variable; if an i IP core and a j IP core are in parallel test, xij is equal to one, and otherwise, xij is equal to zero; tj is the testing time of the j IP core, and the absolute value of M represents the sum of IP cores in the SoC and shows the maximum value of IP core testing time in parallel test; yi represents a binary variable, and the mark number j of the IP core is smaller than the mark number I; if any j IP core and any i IP core are in parallel test, yi is equal to zero, and otherwise, yi is equal to one; and a variable and ui which is equal to yiici are introduced to linearize the mathematical model, and the minimum of T is calculated by an ILP (integer linear programming) tool according to a constraint condition. The method is applicable to three-dimensional SoC testing and scheduling.

Description

technical field [0001] The invention belongs to the technical field of three-dimensional SoC test scheduling. Background technique [0002] In recent years, the increase in the scale of integrated circuits and the reduction in feature size have put forward higher requirements for the integration of chips. Three-dimensional SoC integration generally applies the idea of ​​IP (Intellectual Property) multiplexing. On the basis of traditional two-dimensional SoC, through-silicon vias (Through-Silicon Via, TSV) are used to transmit interlayer signals, and through multi-device interlayer binding The integration of 3D SoC will be completed. [0003] In order to ensure the reliability of 3D SoC, it needs to be designed for testability. Testability design is divided into three parts: test access mechanism (Test Access Mechanism, TAM), test packaging and test scheduling. Different from two-dimensional SoC testing, due to the special structure and integration technology of three-dime...

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Problems solved by technology

[0006] In order to solve the problem that the test time of the three-dimensional SoC cannot be optimized when the three-dimensional SoC contains both coarse-grained and fine-grained IP cores, the present invention proposes a three-dimensional SoC test scheduling method based on hard cores under power consumption constraints

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