pll double edge lock detector

Abstract

A lock signal indicating that the target signal is in phase with the reference signal includes detecting the reference signal on rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out-of-phase condition between the target and reference signals is used to place the timing device in a reset state. Upon allowing the timing means to time out, a signal is asserted indicating that the target signal is considered locked to the reference signal.

Description

[0001] Cross References to Applications [0002] This disclosure claims priority to US Provisional Application No. 61 / 406,953, filed October 26, 2010, the contents of which are hereby incorporated by reference for all purposes. technical field [0003] The present disclosure relates to phase locked loop (PLL) circuits, and in particular to portions of circuits for detecting when the output of the PLL has locked onto a reference signal. Background technique [0004] Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. [0005] Phase-locked loops (PLLs) are widely used in communication electronics and digital electronics. In wireless products, PLLs are often used to generate high-speed system clocks. When powering up the electronics for the PLL, the frequency of the PLL output signal may take on the order of tens of microseconds to be...

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Problems solved by technology

Transistor 228 is turned on, thus capacitor 222 is not charged

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