[0043] Hereinafter, the present invention will be described in detail with reference to the drawings and in conjunction with the embodiments. It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other if there is no conflict.
[0044] For the interrupt controller in the related technology, synchronous sampling is adopted when performing interrupt processing, which easily leads to the risk of loss of sampling signals, and the handshake process is relatively complicated. Based on this, the embodiments of the present invention provide an interrupt processing method, device, and interrupt controller, which simplifies the handshake process and reduces the logic of the interrupt controller, which will be described below through embodiments.
[0045] image 3 Is a flowchart of an interrupt handling method according to an embodiment of the present invention, such as image 3 As shown, the method includes the following steps (step S302-step S304):
[0046] Step S302, the CPU receives the interrupt request sent by the interrupt controller, executes the interrupt corresponding to the interrupt request, and writes a first value to the interrupt controller, the first value is used to indicate that the CPU receives the interrupt request;
[0047] In step S304, after the CPU finishes executing the above interrupt, it writes a second value to the above interrupt controller, and the second value is used to indicate that the CPU finishes executing the above interrupt.
[0048] Through the above embodiment, after the CPU receives the interrupt request sent by the interrupt controller, it executes the interrupt corresponding to the above interrupt request, and writes the first value to the interrupt controller, the first value is used to indicate that the CPU receives the above interrupt request; CPU After the above interrupt is executed, the second value is written to the interrupt controller. This second value is used to indicate that the CPU has completed the above interrupt, which solves the problem of the interrupt controller in related technologies that uses more logic and takes up a large area. The use of asynchronous sampling avoids the loss of interrupt signals, simplifies the software process, and achieves the effect of reducing the logic quantity of the interrupt controller and saving area.
[0049] In this embodiment, the CPU configures the interrupt controller through the APB bus, including configuring the sampling mode, interrupt priority, and interrupt type of each external interrupt source; then, the interrupt controller is enabled; when the CPU receives the interrupt control After saving the interrupt request, immediately write an arbitrary value back to the interrupt ack register of the interrupt controller, indicating that the CPU has received the interrupt request; when the CPU finishes executing the interrupt service subroutine, the interrupt to the interrupt controller is done Write an arbitrary value to the register, which means that the CPU has finished executing the currently executing interrupt.
[0050] Before the CPU receives the interrupt request sent by the interrupt controller, the interrupt controller and the CPU need to be connected first. Therefore, this embodiment provides a preferred embodiment. The interrupt controller includes a bus interface module, which can pass APB The bus is connected to the CPU.
[0051] Before the CPU receives the interrupt request sent by the interrupt controller, the above method further includes: the interrupt sampling module of the interrupt controller asynchronously samples the external interrupt source, and outputs the interrupt signal after the interrupt request is sampled. After the CPU executes the interrupt corresponding to the interrupt request, the above method further includes: the interrupt comparison module of the interrupt controller compares the priority of the interrupt signal output by the interrupt sampling module, and sends the interrupt information of the interrupt with the highest priority to the interrupt control module; The interrupt control module of the controller saves the interrupt information of the nested interrupt and saves the interrupt information of the interrupt currently being executed by the CPU.
[0052] The CPU writing the first value to the interrupt controller includes: after the CPU enters the interrupt service subroutine, the CPU writes the above first value in the interrupt ack register of the interrupt controller; the interrupt control module of the interrupt controller clears the output of the interrupt sampling module The interrupt signal. The CPU writes the second value to the interrupt controller includes: after the CPU completes the interrupt service subroutine, the CPU writes the above second value in the interrupt done register of the interrupt controller; the interrupt control module clears the current saved in the interrupt status register information.
[0053] For the storage process of interrupt information, this embodiment provides a preferred implementation. If the interrupt sent by the interrupt comparison module has a higher priority than the interrupt saved in the interrupt field register, the interrupt field register will send the currently saved information To the stack, the interrupt field register saves the interrupt information of the interrupt sent by the interrupt comparison module, and outputs the interrupt to the CPU; wherein the interrupt control module includes the stack and the interrupt field register;
[0054] If the interrupt sent by the interrupt comparison module is lower than the priority of the interrupt saved in the interrupt field register, the currently executing interrupt will continue to be executed. The interrupt comparison module will continue to keep the above interrupt valid until the interrupt comparison module is higher than the terminal All interrupts with a higher priority are executed, or the above external interrupt source provides an interrupt with a higher priority than the above interrupt.
[0055] Corresponding to the foregoing interrupt handling method, this embodiment provides an interrupt handling device, which is used to implement the foregoing embodiment, Figure 4 Is a structural block diagram of an interrupt processing device according to an embodiment of the present invention, such as Figure 4 As shown, the device includes: an access module 10, a first writing module 20, and a second writing module 30. The structure will be described in detail below.
[0056] The access module 10 is used to receive the interrupt request sent by the interrupt controller;
[0057] The first write module 20, connected to the access module 10, is used to execute the interrupt corresponding to the interrupt request and write a first value to the interrupt controller, where the first value is used to indicate that the interrupt request is received ;
[0058] The second writing module 30 is connected to the first writing module 20 and is used to write a second value to the interrupt controller after the execution of the interrupt is completed, where the second value is used to indicate that the execution of the interrupt is completed.
[0059] Through the above embodiment, after the access module 10 receives the interrupt request sent by the interrupt controller, the first write module 20 executes the interrupt corresponding to the above interrupt request, and writes the first value to the interrupt controller, and the second write module 30 After the above interrupt is executed, the second value is written to the interrupt controller, which solves the problem that the interrupt controller uses more logic and occupies a large area in the related technology. Asynchronous sampling is used to avoid the loss of interrupt signals and simplify The software flow has the effect of reducing the logic quantity of the interrupt controller and saving area.
[0060] The interrupt controller includes an interrupt ack register and an interrupt done register, and the above-mentioned first value and second value can be stored in the interrupt ack register and the interrupt done register, respectively. Specifically, the above-mentioned first writing module 20 includes: a first writing unit, configured to write the above-mentioned first value in the interrupt ack register of the interrupt controller after entering the interrupt service subroutine. The second writing module 30 includes: a second writing unit for writing the second value in the interrupt done register of the interrupt controller after the interrupt service subroutine is executed.
[0061] Figure 5 It is a schematic diagram of the structure of the interrupt controller and the CPU interface according to the embodiment of the present invention, such as Figure 5 As shown, the interrupt controller is connected to the CPU through the APB bus, and the interface between the interrupt controller and the CPU is a standard APB Slave interface.
[0062] Image 6 It is a schematic diagram of the hardware structure of the interrupt controller according to the embodiment of the present invention, such as Image 6 As shown, the interrupt controller includes: a bus interface module (also called an APB bus interface module), an interrupt sampling module, an interrupt comparison module, and an interrupt control module. The functions of the above modules are described below.
[0063] The bus interface module, the function of the module is equivalent to the function of the bus interface module of the foregoing embodiment, and provides a standard APB Slave interface for configuring various parameters of the interrupt controller. It is mainly used to configure the internal registers of the interrupt controller through the APB bus. Through the configuration of these registers, the external interrupt source can be individually shielded and allowed, and the trigger type of the external interrupt source (low level, high level, Rising edge, falling edge), the external interrupt source can be set to normal interrupt (IRQ) or fast interrupt (FIQ), or the interrupt source can be set to soft interrupt mode, that is, to initiate by writing 1 to the corresponding bit of the soft interrupt register Interrupt request. There are two registers in the bus interface module that are used by the CPU to shake hands with the interrupt controller: interrupt ack register and interrupt done register. When the CPU enters the interrupt service subroutine, write an arbitrary value to the interrupt ack register to indicate that the interrupt is received. At this time, the interrupt control module will clear the output of the corresponding interrupt sampling module; when the CPU finishes executing the interrupt service subroutine , Write an arbitrary value to the interrupt done register. At this time, the interrupt control module will clear the current interrupt status register. If it is due to interrupt nesting at this time, the interrupt control module will be popped from the stack and pushed in at the latest The interrupt status of the stack is used to update the interrupt status register.
[0064] Interrupt sampling module, the function of this module is equivalent to the function of the interrupt sampling module of the above embodiment, this module can sample external interrupt sources, Figure 7 It is a schematic diagram of the structure of the interrupt sampling module implementing asynchronous sampling according to the embodiment of the present invention. The module is responsible for sampling the external interrupt source according to the configuration of the bus interface module. When the interrupt sampling module receives a valid interrupt request, it will always output high voltage Until the interrupt control module sends a clear signal, the interrupt sampling module will pull the output signal low. The circuit principle of the above interrupt sampling module is as follows: int_scr[1:0] is a sampling mode configured through the bus, 00 represents low level, 01 represents rising edge, 10 represents falling edge, and 11 represents high level. int_en is the interrupt enable configured through the bus. int_clear is the sampling clear signal from the control module to the sampling module. This signal will be sent out when the CPU receives the interrupt. For level sampling, that is, int_scr[0]==int_scr[1], int_req will be directly output to samplel_result. For edge sampling, that is, int_scr[0]!=nt_scr[1], when the input signal int_req has a transition, trig_reg and trig_reg_d will not be equal, int_gen will be equal to 1, and sent to the D terminal of the sample_result register, sample_result is Will be valid, that is, an edge interrupt request is received.
[0065] Interrupt comparison module, the function of the module is equivalent to the function of the interrupt comparison module of the above embodiment, the output of the interrupt sampling module is compared with priority, and the interrupt with higher priority is output to the interrupt control module. Figure 8 Is a schematic diagram of the structure of an interrupt comparison module according to an embodiment of the present invention, such as Figure 8 As shown, the input interrupt will enter the interrupt comparison module after sampling, and the interrupt comparison module will decide which interrupt to output to the next level of comparison according to the priority of the interrupt configuration. 128 interrupt sources, to compare 7 times (such as Figure 8 ①, ②……⑦) can get an interrupt with the highest priority, and then output to the interrupt control module. The above-mentioned interrupt comparison module compares the interrupt priority according to the interrupt request signal of the interrupt sampling module and the interrupt priority and interrupt type configured by the APB bus, and outputs the interrupt with the highest priority. The interrupt information (such as interrupt number, priority and other information) ) To the interrupt control module.
[0066] Compared with the above-mentioned synchronization method in the related art, the area of the interrupt comparison module in this embodiment is much reduced. Assuming that many mid-range sampling modules are instantiated, a lot of registers can be saved in area. The interrupt controller in this embodiment instantiates 128 interrupt sampling modules, and the modules are asynchronous sampling, no interrupts are lost, and the response is faster.
[0067] Interrupt control module, the function of the module is equivalent to the function of the interrupt control module of the above-mentioned embodiment, the interrupt control module includes a stack to save the information of nested interrupts, and also includes an interrupt field register to save the current execution Information about the interruption. If the interrupt output by the interrupt comparison module has a higher priority than the interrupt saved in the interrupt field register, the information of the interrupt field register enters the stack, the interrupt field register is updated with the interrupt information output by the interrupt comparison module, and the interrupt is output to the CPU. If the interrupt output by the interrupt comparison module is lower than the priority of the interrupt saved in the interrupt field register, the interrupt comparison module continues to keep this output valid until the external interrupt source has a high priority interrupt or the interrupt comparison module has a high priority interrupt. End of execution. This module can compare the interrupt output by the interrupt comparison module with the interrupt currently being executed. If the interrupt output by the interrupt comparison module is lower or equal to the priority of the currently executing interrupt, then continue to execute the currently executing interrupt, if the priority is High, the interrupt of the interrupt comparison module is output, and the current interrupt status enters the stack, and the current interrupt status register is updated with the status of the interrupt output by the interrupt comparison module.
[0068] The CPU in the above embodiment may be a CK610 processor, and other processors only need to be slightly modified according to their own characteristics.
[0069] Picture 9 It is a flowchart of an interrupt processing flow according to an embodiment of the present invention. After receiving an interrupt, the CPU writes an arbitrary number back to the address of 0x24, and the hardware will know that the CPU has received the requested interrupt. When the interrupt is over, the CPU will write an arbitrary number back to the 0x28 address, indicating that the interrupt has been processed. The interrupt controller will automatically push a scene from the stack to update the interrupt controller's interrupt scene register. Picture 9 Except for these two write-backs, which are hardware-related handshake procedures, other operations are required by the CK610 CPU and have nothing to do with the interrupt controller. The following describes the above interrupt processing flow, such as Picture 9 As shown, the process includes the following steps (step S902-step S938).
[0070] In step S902, the abnormal service program starts.
[0071] Step S904, save the program scene.
[0072] Step S906: Write back any number to the 0x24 address of the interrupt controller to clear the interrupt source.
[0073] In step S908, it is judged whether fe==0 is established, if so, step S910 is executed, and if not, step S924 is executed.
[0074] Step S910, pushing the fpsr and fpc registers onto the stack.
[0075] Step S912, the FE bit of the PSR is set.
[0076] Step S914, perform interrupt processing.
[0077] In step S916, the FE bit of the PSR is cleared.
[0078] Step S918, write back an arbitrary number to the 0x28 address of the interrupt controller, indicating the end of the interrupt.
[0079] Step S920, restore the fpsr and fpc registers from the stack.
[0080] In step S922, the interrupted scene is restored, and the rfi command is used to return.
[0081] In step S924, the epsr and epc registers are pushed onto the stack.
[0082] In step S926, the EE and IE of the PSR are set.
[0083] Step S928, perform interrupt processing.
[0084] Step S930, clear the EE and IE bits of the PSR.
[0085] Step S932: Write back any number to the 0x28 address of the interrupt controller, indicating that the interrupt is over.
[0086] In step S934, the epsr and epc registers are restored from the stack.
[0087] In step S936, the interrupted scene is restored, and the rte interrupt is used to return.
[0088] Step S938, the interruption process ends.
[0089] The interrupt controller in the related technology requires software to push the interrupt field register into the stack for storage. The interrupt control module in this embodiment does not have a software process, and the interrupt information is actively stored in the interrupt control module, and the handshake in the related technology The process is realized through the flag signal. The interrupt controller provided in this embodiment only needs to write back the register, which makes the interface simpler.
[0090] It can be seen from the above description that compared with the existing interrupt controller, the present invention occupies fewer resources, simplifies the interface between the interrupt controller and the CPU, and makes the use of the interrupt controller more convenient. The use of asynchronous sampling can avoid the loss of interrupt signals; it reduces the interface between the interrupt controller and the CPU and simplifies the software process. At the same time, due to the new sampling logic, the area of the interrupt controller will be much smaller than other interrupt controllers.
[0091] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Above, alternatively, they can be implemented with program codes executable by the computing device, so that they can be stored in the storage device for execution by the computing device, and in some cases, can be executed in a different order than here. Perform the steps shown or described, or fabricate them into individual integrated circuit modules separately, or fabricate multiple modules or steps of them into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.
[0092] The above are only preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc., made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
