Bit cell with triple patterned metal layer structure

Abstract

A bitlattice with a triple patterned metal layer structure is revealed. Specific embodiments include: providing a first structure as a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure through a first patterning process of a metal layer; through a second patterning process of the metal layer process, providing a second structure different from the first structure and being the second of the word line structure, the ground line structure, the power line structure and the bit line structure; and a third pattern through the metal layer process, providing a third structure which is different from the first structure and the second structure and is the third of the word line structure, the ground line structure, the power line structure and the bit line structure.

Description

technical field [0001] This disclosure relates to the fabrication of miniaturized Static Random Access Memory (SRAM) bit cells. The present disclosure is particularly applicable to SRAM bit cells that can go beyond 20 nanometer (nm) technology nodes (eg, 14 nm and other technology nodes). Background technique [0002] As technology advances, and the dimensions of transistor devices continue to shrink, it becomes increasingly difficult to maintain lithographic printability of designs used to fabricate semiconductor devices. For example, Figure 1A A conventional SRAM bit cell 100 in a SRAM includes a metal 1 bonding pad 101 for a word line, a metal 1 bonding pad 103 for a ground line, and a metal 1 bit line structure 105 , and a metal 2 layer structure 107 . Additionally, bitcell 100 includes active area contacts 109, metal contacts 111, and via 1 structures 113 for completing the various interconnections associated with metal 1 layer structures 101, 103, and 105, and metal ...

AI Technical Summary

Problems solved by technology

Therefore, it becomes increasingly difficult to further reduce the design of the cell 100

In addition, if Figure 1B Another conventional SRAM bit cell 130 shown, a single patterned metal line (eg, metal 1 layer structures 131 and 133) occupies significant space

However, if the height of the cell 130 is reduced (eg, to reduce the footprint), the tip-to-tip spacing (where the tip is the short side of the structure) between the metal 1 layer structures 133, especially are in the same color space, would become too close, which would adversely affect the lithographic printability of the bit 130

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