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A divide-by-two and high-speed multiplexer

A multiplexer and two-frequency divider technology, which is applied in the field of integrated circuits, can solve the problems of sampling errors and the initial phase of the two-frequency divider is uncertain, and achieves the effect of avoiding sampling errors.

Active Publication Date: 2017-01-04
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The embodiment of the present invention provides a frequency divider by two and a high-speed multiplexer to solve the problem of sampling errors due to the uncertain initial phase of the frequency divider by two in the existing high-speed multiplexer

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  • A divide-by-two and high-speed multiplexer
  • A divide-by-two and high-speed multiplexer
  • A divide-by-two and high-speed multiplexer

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Embodiment Construction

[0060] The frequency divider by two and the high-speed multiplexer provided by the embodiment of the present invention control the frequency divider by a set signal. When the set signal is valid, the first output terminal of the frequency divider by two is at the second level. The second output terminal of the two-frequency divider is the first level; and after the setting signal is changed from valid to invalid, the two-frequency divider is controlled on the first active edge of the clock signal received by the two-frequency divider, The first output terminal of the two-frequency divider outputs the first level, and the second output terminal of the two-frequency divider outputs the second level, so that the initial phase of the two-frequency divider is constant, and then the two-frequency divider is used The high-speed multiplexer of the device is correctly sampled.

[0061] The specific implementation manners of a frequency divider by two and a high-speed multiplexer provid...

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Abstract

The embodiment of the invention provides a two-divided-frequency device and a high-speed multiplexer to solve the problem of sampling errors caused by an undetermined initial phase of the two-divided-frequency device in an existing high-speed multiplexer. When a setting signal is valid, a first setting circuit in the two-divided-frequency device loads a first level signal to the input end of a first phase inverter to enable the first output end to be a second level, and loads a second level signal to the input end of a second phase inverter to enable the second output end to be a first level. When the setting signal becomes invalid from valid, during the period after the two-divided-frequency device receives the first action edge of an output time signal and before the two-divided-frequency device receives the second action edge of the output time signal, the first output end of the two-divided-frequency device outputs the first level, the second output end of the two-divided-frequency device outputs the second level, and accordingly the two-divided-frequency clock signal with the determined phase is output.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a frequency divider by two and a high-speed multiplexer. Background technique [0002] In the current ultra-high-speed signal processing, one ultra-high-speed signal is usually decomposed into multiple low-speed signals for digital signal processing. After the processing is completed, the multiple low-speed signals are restored to one ultra-high-speed signal through a high-speed multiplexer. The high-speed multiplexer needs to synthesize N groups of low-speed signals with M channels in each group and each frequency of F into N groups of ultra-high-speed signals with 1 channel in each group and each frequency of M*F. That is to say, Synthesize M channels of low-speed signals with a frequency of F in each group into 1 channel of ultra-high-speed signals with a frequency of M*F. High-speed multiplexers are so named because they can include multiple relatively lower-spee...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K21/00H03K17/693
Inventor 袁俊顾洵高鹏
Owner HUAWEI TECH CO LTD
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