Three-dimensional fan-out type wafer level package structure and manufacturing process

Abstract

The invention relates to a three-dimensional fan-out type wafer level package structure and a manufacturing process. The manufacturing process is characterized in that metal layers are manufactured on a carrying sheet through the process with the front faces of chips facing upwards, grooving is conducted according to the arrangement positions of the chips, electrodes connected with other packaging units are manufactured according to the requirements, the internal structure of a fan-out type wafer level package is changed, rigidity is enhanced, the thermal coefficient of expansion is increased, and warping, slipping and dislocation of a whole wafer are reduced. Rerouting layer manufacturing is conducted on the front faces of the chips after plastic package is conducted, and bonding pads of the chips are fanned out to form first layer chip circuits. Then, the second layer chips are manufactured, the process with the front faces of the chips facing upwards is repeated, the corresponding chip and the corresponding metal layer are pasted on the first packaging unit, and the first packaging unit is connected with the previous packaging unit. Then, the plastic package process, drilling and metal filling are conducted. RDL manufacturing is conducted on the second layer chips. Finally, the multiple layers of chips are stacked by repeating the stacking process, or lower bump metal layers are manufactured on RDL layers, and the complete three-dimensional packaging structure is formed.

Description

technical field [0001] The invention relates to a three-dimensional fan-out wafer-level packaging structure and manufacturing process, belonging to the technical field of semiconductor packaging. Background technique [0002] The three-dimensional fan-out wafer-level packaging can achieve the highest stacking density in the three-dimensional direction, the smallest size, and greatly improve chip speed and low power consumption, but there are also certain defects. At present, it is very difficult to control the warpage of the fan-out packaging using the molding process. The solutions in the prior art are to reduce the warpage from the aspects of material properties and the final shape of the molding; It is also difficult to control the slippage and shift caused by (EMC) expansion and contraction. Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies in the prior art, and provide a three-dimensional fan-out wafer-level packa...

AI Technical Summary

Problems solved by technology

[0002] Three-dimensional fan-out wafer-level packaging can achieve the highest density of three-dimensional stacking, the smallest size, and greatly improve chip speed and low power consumption, but there are also certain defects

At present, it is very difficult to control the warpage of the fan-out packaging using the molding process. The solutions in the prior art are to reduce the warpage from the aspects of material properties and the final shape of the molding; It is also difficult to control the slip and shift caused by (EMC) expansion and contraction

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