LPC peripheral extension method and device based on gpio interface

A technology of peripheral expansion and interface, applied in the direction of instrumentation, electrical digital data processing, etc., to achieve the effect of satisfying flexibility and ensuring reliability

Active Publication Date: 2016-08-03
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, at present, many systems can only be applied in the system through the more complex interface of the South Bridge.

Method used

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  • LPC peripheral extension method and device based on gpio interface
  • LPC peripheral extension method and device based on gpio interface
  • LPC peripheral extension method and device based on gpio interface

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Embodiment Construction

[0035] like figure 1 As shown, the implementation steps of the LPC peripheral expansion method based on the GPIO interface in this embodiment are as follows:

[0036] 1) Based on the bidirectional asynchronous request-response handshake protocol, the message request initiated by the CPU through the GPIO interface is received through multiple handshake transmissions. The optional field information of the message request includes three kinds of information: message header, address and data. The types of message requests include DMA read, DMA write, LPC device read request, and LPC device write request, and the message request of type DMA read or LPC device write request only contains header and address information without data information. , the address information of the message request with the type of DMA read and DMA write is the DMA channel number; parse the message request, and judge the sending target according to the message header of the message request. If the sending ...

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PUM

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Abstract

The invention discloses a method and a device for expanding an LPC (linear predictive coding) peripheral on the basis of a GPIO (general purpose input / output) interface. The method includes primarily communicating the LPC peripheral with the GPIO interface of a CPU (central processing unit) on the basis of a two-way asynchronous request-acknowledge handshake protocol; forwarding received messages to the lower-level LPC peripheral by the aid of a secondary synchronous handshake protocol or interrupting operation on an internal register; reversely initiating interrupt requests to the GPIO interface of the CPU if serial interrupt requests or internal interrupt requests of the LPC peripheral are received. The device comprises a GPIO and LPC interface module, an LPC bus protocol control module and an LPC serial interrupt control module. The GPIO and LPC interface module is connected with the CPU. The method and the device have the advantages that the LPC peripheral can be expanded easily and flexibly, a system can be expanded conveniently, communication is irrelevant to particular clocks, special requirements on a clock of the GPIO interface can be omitted, communication data are reliable, hardware resources can be saved, and the method and the device are transparent for upper-layer users.

Description

technical field [0001] The invention relates to the technical field of peripheral expansion of an embedded system, in particular to an LPC peripheral expansion method and device based on a GPIO interface. Background technique [0002] In the current microprocessor design, some processors, such as THG26F07BD, are designed with an LPC protocol interface, which can be used directly because the interface meets the synchronous interface timing requirements of the LPC protocol specification. However, many other microprocessors are not designed with an LPC interface, so that the LPC interface will not be available in the system. At present, most of the existing processors have GPIO interfaces, but LPC devices cannot be directly used through the GPIO interfaces. This is because the GPIO interface cannot complete effective clock synchronization communication with the LPC device, and even if the GPIO interface operation executes valid commands within the specified period of the rated...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38
Inventor 马爱永张明郭御风邓宇龚锐任巨石伟高正坤窦强
Owner NAT UNIV OF DEFENSE TECH
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