A shared data cache device and control method for multiple coarse-grained dynamically reconfigurable arrays

Abstract

The invention discloses a shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and a control method of the shared data caching device. The shared data caching device comprises a reconfigurable array data caching control unit, a reconfigurable array data caching unit, an external memory data prefetching caching unit and a data memory access reconfiguration unit, wherein the reconfigurable array data caching control unit is used for controlling data interaction between the reconfigurable arrays and the reconfigurable array data caching unit and data interaction between the reconfigurable array data caching unit and an external memory, the reconfigurable array data caching unit is used for storing data fetched from the external memory, the external memory data prefetching caching unit is used for prefetching data to be accessed to the reconfigurable array data caching unit, and the data memory access reconfiguration unit is used for sending address information and step length information needed by the reconfigurable array data caching unit. The control method is used for achieving data sharing between the coarse-grained dynamic reconfigurable arrays in a reconfigurable system. By means of the shared data caching device and the control method, access conflict is reduced, data processing time of the reconfigurable system is shortened, and the calculation performance of large-scale coarse-grained reconfigurable arrays is improved.

Description

technical field [0001] The invention relates to the field of embedded reconfigurable design, in particular to a shared data cache device and control method for multiple coarse-grained dynamic reconfigurable arrays. Background technique [0002] Processors and application-specific integrated circuits (ASICs) are computing platforms in the field of traditional computer system structures. The characteristic of processors is to complete calculations by executing related instructions in the instruction set without changing the underlying hardware environment. But the operation speed of the processor is much slower than that of ASIC, and each independent operation has higher execution overhead. The characteristic of application-specific integrated circuits is that the operation of applications implemented by hardware has high speed, efficiency and precision, but its disadvantages are that the development cycle is too long, the cost is too high, and once the hardware circuit is mad...

AI Technical Summary

Problems solved by technology

[0004] With the improvement of computing performance requirements, the computing complexity is getting higher and higher, and the computing resources of the coarse-grained reconfigurable architecture are also greatly increased. Using multiple reconfigurable arrays to complete these applications, in multiple reconfigurable arrays When accessing data at the same time, it will cause access conflicts, generate access delays, increase data access time, and greatly reduce computing performance.

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