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A method for fabricating self-aligned double-layer graphics with no load on the bottom

A manufacturing method and self-alignment technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as damage to the bottom dielectric layer, loading effect at the bottom, and inability to remove the amorphous carbon film

Active Publication Date: 2017-06-06
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] Since the hard mask layer is used in the above process, the hard mask layer must be removed in the subsequent process, otherwise the amorphous carbon film cannot be removed or there is residual
However, etching away the hard mask layer before removing the amorphous carbon film will damage the bottom dielectric layer, resulting in a loading effect at the bottom
Figure 10 The dotted frame area in the middle is the position of the bottom load, and it can be seen that the self-aligned double-layer graphic structure formed by the existing manufacturing method has a bottom load

Method used

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  • A method for fabricating self-aligned double-layer graphics with no load on the bottom
  • A method for fabricating self-aligned double-layer graphics with no load on the bottom
  • A method for fabricating self-aligned double-layer graphics with no load on the bottom

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Embodiment Construction

[0039] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0040] Below will combine specific embodiment and appended Figure 11-18 The method for fabricating the self-aligned double-layer pattern of the present invention will be further described in detail. Figure 11 It is a schematic flow chart of a method for fabricating a self-aligned double-layer pattern according to a preferred embodiment of the present invention, Figure 12-18 It is a schematic diagram of the cross-sectional structure formed by the specific steps of the method for fabricating the self-aligned double-layer pattern in the above-mentioned preferred e...

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Abstract

The invention provides a manufacturing method of a self-alignment double-layer pattern without loads at the bottom. The manufacturing method comprises the steps that an amorphous carbon film and a hard mask layer are sequentially formed on a medium layer at the bottom; a photoetching process and an etching process are adopted, and the hard mask layer is patterned; the patterned hard mask layer serves as a mask, the amorphous carbon film is etched through the etching process, and the downward etching height is smaller than the thickness of the amorphous carbon film; the hard mask layer is removed in an etching mode; the amorphous carbon film is etched downwards again and stopped on the surface of the medium layer at the bottom; an insulation side wall is formed on the medium layer at the bottom; the amorphous carbon film is removed, and therefore the self-alignment double-layer pattern is formed. The method can effectively prevent damage to the bottom in an existing process, and can be used for manufacturing the self-alignment double-layer pattern without loads at the bottom.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for fabricating self-aligned double-layer graphics with no load on the bottom. Background technique [0002] With the continuous shrinking of process dimensions, especially in 20nm and below technologies, self-aligned double-layer patterning process (SADP) is widely used in the formation of key layer patterns such as active area (AA) and polysilicon (POLY). [0003] Normally, see Figure 1-10 , figure 1 It is a schematic flow chart of an existing self-aligned double-layer pattern manufacturing method, Figure 2-10 It is a schematic diagram of the cross-sectional structure corresponding to the specific steps of the existing self-aligned double-layer graphics manufacturing method, and the specific steps are: [0004] Step L01: See figure 2 , sequentially forming an amorphous carbon film 2' and a hard mask layer 3' on the bottom dielectric layer 1'; [0005] St...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311
CPCH01L21/0338
Inventor 崇二敏朱轶铮黄君
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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