Semiconductor device and method of forming same, non-transitory computer-readable storage medium

Abstract

The invention discloses a semiconductor device, a forming method thereof, and a non-transitory computer-readable storage medium. Specifically disclosed is a method of forming a heterojunction bipolar transistor comprising providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack includes a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench defines the extent of the intrinsic base region and stack. Two regions around the stack form the extrinsic base. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. A bridge connects the two regions. Openings are provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Description

technical field [0001] The present invention relates to semiconductor structures, and more particularly to bipolar complementary metal-oxide-semiconductor (BiCMOS) integrated structures comprising bipolar transistors with self-aligned emitter, base and collector electrodes, formed by selective epitaxy base to bridge the base region. Background technique [0002] In recent years, considerable effort has been devoted to perfecting methods for integrating bipolar and complementary metal-oxide-semiconductor (BiCMOS) technologies on a single wafer. High performance circuits require the ability to combine CMOS and bipolar processes in a single ("BiCMOS") process. For example, CMOS transistors are essentially low power devices with large noise margins that can achieve high packing densities. At the same time, bipolar transistors offer advantages in switching speed and current drive. Bipolar transistors are also characterized by high transconductance which is well suited for driv...

AI Technical Summary

Problems solved by technology

[0003] In addition to the positive effect of enhancing the switching speed of the device, there is the problem that changes in the collector of bipolar transistors have some potentially negative side effects

One problem is that the increased electric field in the collector base space charge region results in an increased avalanche multiplication

The second problem is the increased self-heating of the device

[0004] One of the challenges that arises in integrating MOS and bipolar devices in the same circuit is that the fabrication steps required to form each individual device are often fundamentally different

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