An Isolation Setting Method for Hole Impedance Matching in High Speed ​​Circuit Design

A circuit design and impedance matching technology, applied in computing, electrical digital data processing, special data processing applications, etc., can solve the problems of difficulty in adjustment and isolation, difficulty in ensuring accuracy, and time-consuming, and achieve accurate data, data accuracy and reliability. Effective, discriminative way efficient effect

Active Publication Date: 2017-08-25
P C B A ELECTRONICS WUXI
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Problems solved by technology

However, it is difficult to adjust the isolation in the circuit design software, and it is very time-consuming in terms of size, disk stack, data volume, etc., and the accuracy is difficult to guarantee

Method used

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  • An Isolation Setting Method for Hole Impedance Matching in High Speed ​​Circuit Design

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Embodiment Construction

[0022] The present invention will be further described below in conjunction with drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only parts related to the present invention are shown in the drawings but not all content.

[0023] Please refer to figure 1 as shown, figure 1 A flow chart of an isolation setting method for hole impedance matching in high-speed circuit design provided by an embodiment of the present invention.

[0024] In this embodiment, the isolation setting method for hole impedance matching in high-speed circuit design includes the following steps:

[0025] Step S101, start, initialize the stack structure, keep the polarity and depth of each layer of the stack hole independent, this situation may include hole stack information such as blind holes, back ...

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Abstract

The invention discloses an isolating setting method of pore impedance matching in a high-speed circuit design. According to the method, pores needing to be subjected to isolating setting are screened out through modes of network selection, group selection and point selection. The method includes the following two selective modes that (1) partial layers are selected and subjected to isolating setting according to mapped cascades; (2) all the settable cascades of target pores are defined and are subjected to isolating setting. Meanwhile, effective parameter setting of oval isolation is provided, and precise and effective data are guaranteed. By means of the method, selection, parameter setting and differentiating in the operation process are efficient and precise, and extraction of parameters and mapping of the cascades both simulate the modeling steps in the simulation process, so that data are more precise, in particular, in the high-speed backboard designing process, the advantages of convenience and high efficiency of the method are manifested when thousands of pores are subjected to isolating setting by means of the method.

Description

technical field [0001] The invention relates to the field of high-speed circuit design, in particular to an isolation setting method for hole impedance matching in high-speed circuit design. Background technique [0002] At present, digital circuits of 100M and above are very common in the industry, and the impedance matching problem of holes in the design of high-speed circuits of this rate and above can no longer be ignored. Usually this kind of design process is: use the simulation method to determine the isolation size; adjust the hole to copper spacing according to the simulation results. In order to achieve the purpose of adjusting impedance matching. However, it is difficult to adjust the isolation in the circuit design software, and it is very time-consuming in terms of size, disk stack, data volume, etc., and the accuracy is difficult to guarantee. Contents of the invention [0003] The purpose of the present invention is to solve the problems mentioned above in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 陈懿陈传开应朝晖王锡刚刘鹍刘进军
Owner P C B A ELECTRONICS WUXI
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