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Wafers and their acceptable test methods

A test method and wafer technology, applied in the direction of electrical components, electric solid state devices, circuits, etc., can solve the problems of positioning deviation, the probe cannot accurately land on the test point, and the chip is scratched.

Active Publication Date: 2017-08-08
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in the traditional WAT method, because the alignment accuracy of the probe program is not enough, when the alignment pattern in the scribing groove is relatively close, if the alignment pattern is misidentified, it will lead to positioning deviation
In this way, the probe cannot fall on the test point accurately, and scratch other parts of the wafer, resulting in the scrapping of the wafer

Method used

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  • Wafers and their acceptable test methods
  • Wafers and their acceptable test methods
  • Wafers and their acceptable test methods

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0017] Such as figure 1 Shown is a schematic diagram of a wafer of an embodiment. The wafer 10 includes wafers 100 formed thereon and arranged in a matrix, the wafers 100 being divided into a plurality of test areas 200 . The test area 200 can be divided according to test requirements or by functional areas. Each test area 200 includes at least four wafers 100 arranged in a matrix.

[0018] Such as figure 2 shown, is figure 1 Partial enlarged view of part A in middle. In the wafer 10 , the wafers 100 are not closely arranged, but have a distance of 60-100 microns between each other, that is, dicing grooves or subscribe lines. In the wafer 10 of this embodiment, two alignment patterns 202 and 204 are provided in the scribe grooves in each test area 200 , and are respectively arranged in the horizontal scribe grooves and the vertical scribe grooves. The positions of the alignment patterns in other test areas 200 can be set with reference to Part A.

[0019] The above-men...

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PUM

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Abstract

The invention discloses a wafer, which includes wafers formed thereon and arranged in a matrix, the wafer is divided into a plurality of test areas, each test area contains at least four wafers arranged in a matrix, and each test The interval area between the wafers in the area forms a scribe groove located in the test area, and at least two alignment patterns are arranged in the scribe groove in each test area, and in the lateral scribe groove and At least one alignment pattern is respectively arranged in the longitudinal scribe grooves. Also disclosed is a wafer acceptance testing method, using the above arrangement to align the pattern in the horizontal and vertical scribe grooves to position the test area. The above-mentioned wafer and testing method can effectively avoid damage to the wafer caused by misidentifying the alignment pattern.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer acceptance testing method and a wafer. Background technique [0002] WAT (wafer acceptance test, wafer acceptance test) is an important step in the chip manufacturing process. It is used to detect whether the chip on the wafer meets the expected design goals, that is, whether the electrical parameters of the chip meet customer needs. [0003] WAT is carried out in blocks, and one area is tested at a time. A region contains a plurality of dies, and the plurality of dies are spaced apart from each other, and the space between the dies is called a dicing groove or a subscribe line. In order to accurately locate the position of the test area, some alignment patterns are generally arranged on the wafer to assist alignment. The alignment pattern is arranged in the above-mentioned scribe groove, and its pattern is completely different from the circuit patte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/68
Inventor 连晓谦凌耀君
Owner CSMC TECH FAB2 CO LTD