Board-level circuit testability index calculation method

An index calculation, board-level circuit technology, applied in the direction of calculation, electrical digital data processing, special data processing applications, etc., can solve the problem that the test index cannot be calculated, and the relationship between the test and the fault location is not reflected.

Inactive Publication Date: 2014-09-24
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

Compared with the multi-signal flow method, the matrix D u It does not reflect the positional relationship between tests and faults. In addition, due to the many-to-many relationship between tests and faults, testability indicators (such as fault isolation) cannot be directly ca

Method used

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  • Board-level circuit testability index calculation method
  • Board-level circuit testability index calculation method
  • Board-level circuit testability index calculation method

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Embodiment Construction

[0031] Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0032] figure 1 It is a schematic flow chart of the specific implementation of the board-level circuit testability index calculation method of the present invention. Such as figure 1 As shown, the method for calculating the testability index of the board-level circuit of the present invention includes the following steps:

[0033] S101: Build a dependency matrix D independent of signal flow u :

[0034] According to the test information database, including device types, failure probability of various devices, failure modes, probability of each failure mode, test items, ...

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Abstract

The invention discloses a board-level circuit testability index calculation method which comprises the following steps: constructing a dependency matrix Du irrelevant with the signal flow and position by virtue of combining device information in a circuit according to a test information database; calculating according to the dependency matrix Du to obtain the maximal fault detection rate; reconstructing the dependency matrix Du to obtain a restructuring matrix; realizing isolation of devices at different positions in similar devices; calculating according to the restructuring matrix so as to obtain the maximal failure isolation rate; calculating the failure isolation rate selected by the current test according to the Boolean vector selected by the test. Therefore, by virtue of construction and reconstruction of the Dependency matrix Du irrelevant with the signal flow, calculation of various testability indexes in a board-level circuit is realized.

Description

technical field [0001] The invention belongs to the technical field of board-level circuit fault testing, and more specifically relates to a method for calculating testability indexes of board-level circuits. Background technique [0002] The system-level testability indicators of board-level circuits include commonly used data in board-level circuit testing, including the highest fault detection rate (FDR), the highest fault isolation rate (FIR), and the fault isolation rate of the currently selected test. Most of the commonly used system-level testability index calculation methods are based on the dependency matrix (D matrix). The D matrix is ​​obtained from the multi-signal flow diagram of the system under test, which reflects the relationship between signal flow, test and failure modes, failure modes, and high-order dependencies between tests. The general process of obtaining the D matrix is: manually establish a multi-signal flow diagram, generate high-order dependenci...

Claims

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Application Information

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IPC IPC(8): G06F19/00
Inventor 杨成林田书林刘震龙兵
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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