Board-level circuit testability index calculation method

Abstract

The invention discloses a board-level circuit testability index calculation method which comprises the following steps: constructing a dependency matrix Du irrelevant with the signal flow and position by virtue of combining device information in a circuit according to a test information database; calculating according to the dependency matrix Du to obtain the maximal fault detection rate; reconstructing the dependency matrix Du to obtain a restructuring matrix; realizing isolation of devices at different positions in similar devices; calculating according to the restructuring matrix so as to obtain the maximal failure isolation rate; calculating the failure isolation rate selected by the current test according to the Boolean vector selected by the test. Therefore, by virtue of construction and reconstruction of the Dependency matrix Du irrelevant with the signal flow, calculation of various testability indexes in a board-level circuit is realized.

Description

technical field [0001] The invention belongs to the technical field of board-level circuit fault testing, and more specifically relates to a method for calculating testability indexes of board-level circuits. Background technique [0002] The system-level testability indicators of board-level circuits include commonly used data in board-level circuit testing, including the highest fault detection rate (FDR), the highest fault isolation rate (FIR), and the fault isolation rate of the currently selected test. Most of the commonly used system-level testability index calculation methods are based on the dependency matrix (D matrix). The D matrix is ​​obtained from the multi-signal flow diagram of the system under test, which reflects the relationship between signal flow, test and failure modes, failure modes, and high-order dependencies between tests. The general process of obtaining the D matrix is: manually establish a multi-signal flow diagram, generate high-order dependenci...

AI Technical Summary

Problems solved by technology

Compared with the multi-signal flow method, the matrix D u It does not reflect the positional relationship between tests and faults. In addition, due to the many-to-many relationship between tests and faults, testability indicators (such as fault isolation) cannot be directly calculated based on this matrix

In addition, the same test has different test coverage for different chips (or modules), and different tests have different test coverage for the same chip. How to optimize this many-to-many relationship with different fault coverage is another problem

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