How to make sige source/drain region

Abstract

The invention discloses a manufacturing method for a SiGe source / drain region. The method comprises the steps of providing an N-type chip silicon substrate with a formed grid, etching the N-type chip silicon substrate to form a groove of the source / drain region, depositing a metal film on a chip, depositing a Ge film on the metal film, carrying out the annealing process on the chip, enabling Ge atoms in the Ge film to be diffused to the interface between the metal film and the silicon substrate and combined with Si through metal induction crystallization so that a SiGe film can be formed, and removing the metal film and the Ge film on the surface to form a PMOS source / drain region with SiGe. According to the method, the temperature of generating the SiGe film can be effectively lowered, the quality of the SiGe film is improved, and therefore the yield and the performance of devices are promoted.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a method for manufacturing SiGe source / drain regions. Background technique [0002] With the development of semiconductor integrated circuits, the size reduction of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has continuously improved the speed, performance, density and functional unit cost of integrated circuits. After entering the 90nm technology era, with the substantial reduction in the size of integrated circuit devices, the junction depth of the source / drain (elevated source / drain) is getting shallower and shallower, and it is necessary to use selective epitaxy technology (selective epi SiGe, abbreviated as SEG) to increase The thick source / drain serves as a sacrificial layer for subsequent silicide reactions, thereby reducing series resistance. [0003] For the 65 / 45nm technology process, a method to improve...

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Problems solved by technology

[0006] The disadvantages of using the above-mentioned existing SEG method to form SiGe source / drain regions mainly include two aspects: (1) As the technology nodes gradually become smaller, the Ge content requirements are getting higher and higher, and the critical thickness of SiGe is getting thinner and thinner, resulting in the SEG method The defects in the deposited SiGe film increase sharply and the stress decreases, which is not conducive to the improvement of device performance; (2) The growth temperature of the SEG method is generally above 600 ° C, which brings challenges to the thermal budget of small-sized CMOS devices

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