A Linearized Common-Gate CMOS Low Noise Amplifier Circuit

Abstract

The invention discloses a linearization common-gate CMOS low-noise amplifier circuit which is of a differential symmetrical structure and comprises an input stage (M1), a cascading stage (M2) and a distortion eliminating stage (M1a). A radio frequency differential signal is inputted from the input stage, an amplified differential output signal is outputted from the cascading stage, the distortion eliminating stage is connected to the cascading stage, and a PMOS transistor working in a weak inversion area is formed. The linearization common-gate CMOS low-noise amplifier circuit has the advantages that the linearity of LNA can be obviously improved, and meanwhile the performance of being high in gain and low in noise can be achieved.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a low-noise amplifier design technology. Background technique [0002] The scaling down of the CMOS process allows us to easily design low-noise, low-power amplifiers. However, the linearity of CMOS transistors deteriorates due to supply voltage scaling and mobility degradation, a challenge that has given rise to several linearization techniques. [0003] Back in the day, the most effective linearization method among them was Multi-Gate Transistor (MGTR) technology (i.e., T.W.Kim, B.-K.Kim, and K.-R.Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,"IEEE J.Solid-State Circuits,vol.39,no.1,pp.223–229,Jan.2004), such as figure 1 As shown, this technology offsets the negative third-order nonlinear coefficient of the main transistor by paralleling an auxiliary transistor that works in the weak inversion region and ...

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Problems solved by technology

Nonetheless, at high frequencies, the interaction of the second-order nonlinear coefficients and the input network often limits the practical effectiveness of the technique

Therefore, an improved derivative superposition method was proposed to alleviate the contradiction, but it was accompanied by the complexity of the input matching network structure

After that, post-distortion technology appeared (Tae-Sung Kim, Byung-Sung Kim, Post-linearization of cascode CMOSlow noise amplifier using folded PMOS IMD sinker, IEEE Microwave and Wireless Components Letters, VOL.16, NO.4, 2006), such as figure 2 As shown, the control voltage of the third-order intermodulation product IM3 canceller can be sampled from the output node of the common-source input transistor, and the result simplifies the impact on the input matching network, however, its fundamental current leakage makes this technique gain falling problem

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