Method and device for reading length of data block of cache memory in self-adaption mode

Abstract

The invention provides a method and device for reading the length of a data block of a cache memory in a self-adaption mode. The method includes the steps that when the last Cache of a processor is missed, cache data information of the Cache is obtained; whether the missed memory access address and the address of cached data in the Cache are centralized or not is judged according to the cache data information; if yes, the read data length adapting to the data distribution concentration ratio is determined, wherein the line number of the Cache serves as the unit; the processor reads the data to the Cache from the memory with the missed memory access address as the center and according to the determined read data length. The technical problem to be solved through the method and device is to increase the processing speed of a CPU.

Description

technical field [0001] The invention relates to the electronic field, in particular to a data block length adaptive reading method and device of a cache memory. Background technique [0002] With the rapid development of semiconductor technology and computer technology, the gap between the main frequency of the processor and the frequency of the memory is getting wider and wider, resulting in a more serious memory wall problem, which has become one of the major obstacles to performance improvement in computer systems. Among them, the memory wall refers to the phenomenon that the read and write performance of the memory severely restricts the full performance of the processor. [0003] In order to reduce the adverse effects of the speed gap between the processor (CPU) and the memory, modern computer architectures widely adopt the method of setting up a cache memory (Cache) between the CPU and the memory, which may be used in a short period of time. Reused instruction code or...

AI Technical Summary

Problems solved by technology

With the development of semiconductor technology, processors can integrate larger and larger last-level Cache, and there are many specific applications that access continuous or dense memory space addresses, so that in this case, the capacity of a single Cache line There is a phenomenon that the locality of the data space to be accessed cannot be fully utilized, so that it is frequently necessary to read data from the memory to the Cache, which increases the number of CPU pauses and reduces the processing speed of the CPU, resulting in poor overall computer performance.

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