Unlock instant, AI-driven research and patent intelligence for your innovation.

A low parasitic inductance gan power integrated module with split capacitor middle layout

A technology of low parasitic inductance and split capacitance, which is applied in the direction of circuits, electrical components, and electric solid-state devices, etc. It can solve the problems of circuit voltage spikes, large substrate thickness, oscillation, etc., to reduce area, reduce parasitic inductance, avoid oscillation and spike effect

Active Publication Date: 2017-04-26
XI AN JIAOTONG UNIV
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the aluminum oxide substrate can only be wired in a single layer or double layer, and the thickness of the substrate is relatively large, which brings great challenges to the wiring
On the alumina substrate, the power loop inductance of the optimal wiring structure is about 1.2nH, which will bring serious voltage spikes and oscillations to the circuit

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A low parasitic inductance gan power integrated module with split capacitor middle layout
  • A low parasitic inductance gan power integrated module with split capacitor middle layout
  • A low parasitic inductance gan power integrated module with split capacitor middle layout

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0020] In the GaN power integrated module of the present invention, the upper bridge arm device 1, the lower bridge arm device 2 and the bus capacitor 3 are connected in sequence to form a high-frequency power circuit. The upper bridge arm device 1 and the lower bridge arm device 2 are placed in parallel and side by side. The chip bus capacitor is placed between the device 1 of the upper bridge arm and the device 2 of the lower bridge arm. All the sources of the upper bridge arm device 1 and all the drains of the lower bridge arm device 2 are directly connected respectively, and one drain of the upper bridge arm device 1 and one source of the lower bridge arm device 2 are respectively connected to a bus capacitor two electrodes. The specific instructions are as follows:

[0021] like figure 1 As shown, the upper bridge arm device 1 , the lower bridge...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a GaN power integrated module with low parasitic inductance in the middle layout of split capacitors, including an upper bridge arm device, a lower bridge arm device, and a bus capacitor. The upper bridge arm device and the lower bridge arm device are GaN devices packaged in LGA, and the bus bar capacitor It is a chip package. Two GaN devices are placed side by side, and multiple bus capacitors are placed between the two GaN devices. Each source pin of the high-bridge device is directly connected to a drain of the low-bridge device, and each drain of the high-bridge device and a source of the low-bridge device are respectively connected to two bus capacitors. electrode. The layout mode adopted by the present invention can effectively reduce the area of ​​the high-frequency power loop, and at the same time fully utilize the structure of the staggered arrangement of the drain and source pins of the LGA package to form a plurality of interleaved parallel high-frequency power current loops, thereby The parasitic inductance of the high-frequency power loop is significantly reduced, and the overvoltage and oscillation during the switching process are reduced.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and in particular relates to a low parasitic inductance GaN power integration module arranged in the middle of split capacitors. Background technique [0002] GaN power devices are popular new material devices that have appeared in recent years and have been gradually commercialized. Compared with Si devices, they have superior on-state characteristics and very good switching characteristics, so they have attracted the attention of the industry in a relatively short period of time. , Scholars engaged in applied research have also carried out a lot of research work, applying it to low-voltage, low-power power supply devices such as POL and DC / DC. Studies have shown that replacing Si devices with GaN devices can greatly increase the switching frequency while maintaining good efficiency indicators. Undoubtedly, in low-voltage and low-power applications, GaN devices will be more and more w...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/64H01L23/488H01L25/00
Inventor 王康平杨旭曾翔君马焕余小玲郭义宣
Owner XI AN JIAOTONG UNIV