A low parasitic inductance gan power integrated module with split capacitor middle layout
A technology of low parasitic inductance and split capacitance, which is applied in the direction of circuits, electrical components, and electric solid-state devices, etc. It can solve the problems of circuit voltage spikes, large substrate thickness, oscillation, etc., to reduce area, reduce parasitic inductance, avoid oscillation and spike effect
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[0019] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0020] In the GaN power integrated module of the present invention, the upper bridge arm device 1, the lower bridge arm device 2 and the bus capacitor 3 are connected in sequence to form a high-frequency power circuit. The upper bridge arm device 1 and the lower bridge arm device 2 are placed in parallel and side by side. The chip bus capacitor is placed between the device 1 of the upper bridge arm and the device 2 of the lower bridge arm. All the sources of the upper bridge arm device 1 and all the drains of the lower bridge arm device 2 are directly connected respectively, and one drain of the upper bridge arm device 1 and one source of the lower bridge arm device 2 are respectively connected to a bus capacitor two electrodes. The specific instructions are as follows:
[0021] like figure 1 As shown, the upper bridge arm device 1 , the lower bridge...
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