Method for forming shallow trench isolation structure

Abstract

Embodiments of the invention include a shallow trench isolation (STI) structure and methods of forming the same. A trench is formed in the substrate. Silicon oxide and silicon liner layers are formed on the sidewalls and bottom of the trench. A flowable silicon oxide material is filled in the groove, the flowable silicon oxide material is cured, and then the cured flowable silicon oxide material is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in the fabricated device includes a bottom with silicon oxide and a top with silicon oxide liners and silicon liners on the sidewalls additionally.

Description

technical field [0001] The present invention generally relates to methods of fabricating semiconductor devices, and more particularly, to methods of fabricating shallow trench isolation structures. Background technique [0002] Typically, shallow trench isolation (STI) is used to separate and isolate active regions on a semiconductor wafer from each other. These STIs have historically been formed by etching trenches (sometimes called gaps), overfilling the trenches with a dielectric such as oxide, and then removing any excess dielectric with a process such as chemical mechanical polishing (CMP) or etching to The dielectric outside the trench is removed. The dielectric helps to electrically isolate the active regions from each other. [0003] However, as circuit densities continue to increase, the width of these gaps decreases, increasing the gap's aspect ratio, which is typically defined as the gap height divided by the gap width. Therefore, it is very difficult to comple...

AI Technical Summary

Problems solved by technology

Therefore, it is very difficult to completely fill these narrow and deep gaps with gap-filling dielectric materials

Incomplete filling results in undesired voids and discontinuities in the gap-filling dielectric material and inclusions of undesired material

These voids and inclusions lead to insufficient isolation between active regions

Devices with insufficient isolation have poor electrical performance and reduce device yield

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