Processing device and method for write merging and write undo in simd processor

Abstract

The invention provides a writing merging and writing undo processing device and method in an SIMD (single instruction multiple data0 processor. The processing device is characterized in that a system structure register file is used as an operating code storage part of an instruction and connected to an execution unit of the processor; the output of a mark table is connected to a mark allocation unit; the mark allocation unit allocates a mark to the instruction which needs to be written back to a register from the mark table, the mark is different from the mark which is allocated by the instruction and already enters an assembly line and outputted and connected to a mark register file; a writing signal of a target register generated by a decoding logic controls the mark allocated by the mark allocation unit to be written into the mark register file. By adopting the processing device and method, the execution efficiency of the SIMD structure processor can be improved, and the complexity for designing a compiler is alleviated or hardly increased.

Description

technical field [0001] The invention is applicable to the field of processor architecture design, and relates to the design of write-back logic of instruction results supporting write merge and write undo in SIMD structure processors. Background technique [0002] In the current processor design, on the one hand, the instruction set design provides more instruction support, such as multiply-accumulate instructions provided by DSP processors, single-precision floating-point instructions provided by processors that support floating-point calculations, and even extended-precision floating-point instructions. Operation instructions; on the other hand, in order to increase the main frequency of the processor, the pipeline of the processor is further subdivided, and even more than ten stages of pipeline operations are required to complete the execution of a complex instruction. In order to improve the instruction execution efficiency of the processor, the pipeline segment division...

AI Technical Summary

Problems solved by technology

Multiple instructions in the pipeline submit the execution results of the execution instructions at the same time, and the destination registers written back by the instructions are the same set of registers or different sets of registers in the SIMD structure. Due to the limitation of the register port, only one instruction can be written into the register at a time, resulting in write resource conflict

[0005] 2. Write-after-write conflicts

Especially for processors that support the SIMD structure, depending on the degree of parallelism, the execution result of an instruction will write to multiple registers, which greatly increases the logical complexity of detection and de-correlation

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