A kind of preparation method of tunneling field effect transistor

Abstract

The invention discloses a production method of a tunneling field-effect transistor and belongs to the field of CMOS (complementary metal-oxide-semiconductor transistor) ULSI (ultra-large scale integrated circuits) and their field-effect transistor logic devices. According to the production method, a p-type silicon wafer of relative high impedance is used as a trench region and a body region of a TFET (tunneling field-effect transistor) device, a mask for injection of an N<-> region is added on basis of the standard CMOS-IC process, the N<-> region injected deep in a trench, device isolation is achieved for the TFET in circuit application, and device performances and device area are unaffected.

Description

Technical field

[0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra-large integrated circuits (ULSI), and specifically relates to a method for isolating tunneling field effect transistors (TFET). Background technique

[0002] As the size of the MOSFET enters the nanometer scale, the negative effects such as the short channel effect of the device have become more serious, and the off-state leakage current of the device has been increasing. At the same time, because the sub-threshold slope of the traditional MOSFET is limited by the thermoelectric potential, it cannot decrease simultaneously with the shrinking of the device size. There is a theoretical limit of 60mV / dec, which makes the leakage current further increase with the shrinking of the power supply voltage. Increased device power consumption. The power consumption problem has now become one of the most severe problems restricting the scaling of devices. In the fie...

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