A method and device for data processing

Abstract

The invention discloses a data processing method, comprising: calculating the mask of the data segment according to the start address and the length of the data segment requested by the read request; Address and mask associated equality detection relationship, detect the data segment from the write request queue; when the data segment is in the write request queue, obtain the data segment from the write request queue according to a preset scheme the data segment. The embodiment of the present invention also provides a corresponding device. The technical scheme of the invention can determine whether the data segment requested by the read request is in the write request queue through the equal comparator, thereby reducing overhead and improving comparison speed.

Description

technical field [0001] The present invention relates to the technical field of data processing, in particular to a data processing method and device. Background technique [0002] In existing memory controllers, read and write requests are usually scheduled within a certain time window to improve performance. Since read requests often have a more critical impact on performance, write requests are temporarily cached and read requests are processed first, and write requests are not processed until the depth of the write request queue reaches a certain critical value. Each read request should return the most recently written data segment. Since write requests are cached, the latest data segment may not be in memory, but cached in the write request queue of the memory controller. In this way, every time a read request is processed, it must be checked whether its corresponding data segment is cached in the write request queue. [0003] In a traditional memory system, read and ...

AI Technical Summary

Problems solved by technology

The logic resource consumption of the size comparator is large, and the carry logic is required, and the delay is much larger

Especially when the write request queue of the memory controller is long, each cached write request requires such a comparison circuit, and the area, delay, and power consumption are very expensive.

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