Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories

Abstract

A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).

Description

technical field [0001] The present application relates to error detection, in particular in semiconductor memories, and in particular to a circuit arrangement and a method for error detection of permanent errors in memories using a modified error syndrome. Background technique [0002] Due to the increasing integration of semiconductor memories, the frequency of errors in the memories is increasing. [0003] Semiconductor memories are also increasingly used in safety-critical applications, for example in the automotive sector, where the correct mode of function is required. [0004] In order to make the used memory as error-free as possible, an offline test is usually carried out before the memory is used. In this case, a specific test sequence is entered into the semiconductor memory and the actual test response is compared with the expected test response. If it is determined that the actual and expected test responses do not match, the memory is at fault. In this case, ...

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Problems solved by technology

[0013] Restoring original application data via the bus is very time consuming

Furthermore, such tests, which are usually carried out via a CPU (Central Processing Unit, Central Processing Unit), are usually not suitable enough for simulating critical conditions during active operation, since the CPU accesses the memory during the test via a slow bus with wait cycles, i.e. have cycles that do not access memory, but a module using that memory may access that memory in every cycle or in multiple consecutive cycles

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