Method for Enhancing Leakage of Bit Line Defects in Memory Array

A storage array and bit line technology, used in static memory, instruments, etc., can solve problems such as data reading errors, and achieve the effect of improving accuracy and ensuring quality

Active Publication Date: 2018-10-19
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the technical solutions in the prior art cannot effectively deal with the potential defects between the bit lines, which will cause the potential defects between the bit lines to appear in the future use due to cyclic reading and writing, and then cause data reading error etc.

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  • Method for Enhancing Leakage of Bit Line Defects in Memory Array

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Embodiment Construction

[0028] The present invention will be described in more detail and complete below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only parts related to the present invention are shown in the drawings but not all content.

[0029] Flash memory (Flash Memory) is a non-volatile memory, even if the power is turned off, the data will not be lost. The memory cell of flash memory is a three-terminal device and has the same names as a field effect transistor: source, drain, and gate. The difference between flash memory and FET is that there is a floating gate in flash memory, which is set between the control gate and the substrate; there is a silicon dioxide insulating layer between the control gate and the silicon substrate to protec...

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Abstract

The invention relates to the technical field of semiconductor storage, and particularly relates to a method for enhancing electric leakage of storage array bit line defects. The method comprises: programming a storage array to form a checkerboard test pattern, wherein the formed checkerboard test pattern is the distribution of high threshold voltage storage cells and low threshold voltage storage cells formed by orderly arranging, in an interval manner, the high threshold voltage storage cells and the low threshold voltage storage cells formed in the storage array; forming high levels and low levels between adjacent bit lines and between adjacent word lines of the storage array; keeping the high levels and the low levels formed between adjacent bit lines and between adjacent word lines of the storage array for a period, and enhancing the electric leakage of potential defects between the bit lines according to the voltage difference between the high levels and the low levels formed between adjacent bit lines. With the technical scheme, the method of the invention enhances the electric leakage of potential defects between bit lines, enables the electric leakage to be detected during the detection stage, and improves the accuracy of data reading by the storage.

Description

technical field [0001] The invention relates to the technical field of semiconductor storage, in particular to a method for enhancing defect leakage of bit lines of a storage array. Background technique [0002] With the development of semiconductor storage technology, the production process of memory is becoming more and more mature, and semiconductor memory is also developing in the direction of smaller scale and greater integration. In the semiconductor production process, due to the high requirements and high precision of the production process, there will often be a certain number of defective products. For defective products, some defects are more obvious, and can be detected during inspection and then repaired or discarded; but for some defects, they are often not detected during inspection, and will only be revealed after repeated erasing and writing in the future come out. For the defects between the bit lines of the storage array, one of them is that relatively o...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G11C29/04G11C29/10
Inventor洪杰苏如伟王林凯
OwnerGIGADEVICE SEMICON (BEIJING) INC