High-voltage device and low-voltage device integrated structure and integrated method

Abstract

The invention discloses a high-voltage device and low-voltage device integrating structure. A high-voltage device and a low-voltage device are integrated on a same P-type silicon substrate. A P-type suspended deep well having the same area as the silicon substrate is formed in the silicon substrate. An N-type deep well is formed in part of the area of the silicon substrate. The N-type deep well is disposed on the top of the P-type suspended deep well and contacts the P-type suspended deep well. A channel region, a drain expansion region and an isolated well region of the high-voltage device are composed of the same N-type wells or P-type wells as the low-voltage device. In the region beyond the N-type deep well, the P-type suspended deep well can isolate the N-type wells on the top thereof. The N-type deep well can isolate the P-type wells on the top thereof. The invention further discloses a high-voltage device and low-voltage device integrating method. The high-voltage device and the low-voltage device can be integrated with low cost and without the need for new implantation masks, the parameters of the low-voltage device can be kept unchanged, the width of the isolation region between low-voltage devices can be reduced, the device area can be reduced, and the latch-up effect of the whole circuit can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an integrated structure of a high-voltage device and a low-voltage device. The invention also relates to a high-voltage device and a low-voltage device integration method. Background technique [0002] Low-voltage devices are CMOS devices, including NMOS tubes and PMOS tubes; such as figure 1 As shown, it is a structural schematic diagram of an existing low-voltage device; a well region 102 is formed on a P-type silicon substrate 101, and the well region 102 is used as a channel region. For an NMOS transistor, the well region 102 is a P well; PMOS transistor, the well region 102 is an N well. A field oxygen isolation structure 103 is formed on the silicon substrate 101, and an active region is isolated by the field oxygen isolation structure 103. The field oxygen isolation structure 103 is a local field oxygen isolation structure (LOCOS) or a shallo...

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Problems solved by technology

Because the junction depths of the P-type well region 106 and the N-type well region 102 are equivalent, within the junction depth range of the P-type well region 106, the distance between the depletion lines of two adjacent N-type well regions 102 is relatively small. But at the bottom of the P-type well region 106, the doping of the bottom is the P-type doping of the silicon substrate 101, and the doping concentration is relatively light, so that the depletion at the bottom of the P-type well region 106 The range of the region is relatively large, and the distance between the depletion lines of two adjacent N-type well regions 102 is relatively small.

When the depletion lines of the two adjacent N-type well regions 102 at the bottom of the P-type well region 106 are connected so that the two adjacent N-type well regions 102 are connected to each other, in order to avoid the two The penetration between two adjacent N-type well regions 102 needs to make the width of the field oxygen isolation structure 103a between two adjacent N-type well regions 102 larger, which will make the area of ​​the device too large. Big

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