Semiconductor device and formation method

Abstract

Disclosed are a semiconductor device and a formation method. The formation method of the semiconductor device includes the following steps: forming grooves in a semiconductor substrate between adjacent gate structures and using a selective epitaxy technology to form epitaxy layers with a projection morphology on the surfaces of the bottoms of the grooves; processing the epitaxy layers so that insulating layers are formed; and forming stress layers in the grooves, wherein the stress layers are used as source and drain regions. The insulating layers are capable of reducing the leakage current between channel regions of two adjacent MOS transistors and because the epitaxy layers have a projection morphology, the stress layers corresponding to the middle positions of the grooves are smaller in thickness and the stress layers corresponding to the side-wall positions of the grooves are larger so that reduction of the leakage current between the channel regions of the two adjacent MOS transistors is facilitated and a stress action generated by the stress layers on the channel regions of the MOS transistors is not affected.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a semiconductor device and a forming method. Background technique [0002] In the field of semiconductor manufacturing, with the development of integration and miniaturization of semiconductor devices, in order to further improve chip utilization and increase chip integration, in some semiconductor devices, several MOS transistors are arranged side by side and reduced by sharing source and drain regions. occupied chip area. [0003] Please refer to figure 1 , is a schematic cross-sectional structure diagram of a semiconductor device in which multiple MOS transistors share a source region and a drain region in the prior art, including: a semiconductor substrate 10, a plurality of gate structures 11 arranged in parallel on the surface of the semiconductor substrate 10, located on the The trenches (not shown) in the semiconductor substrate 10 on both sides of the gate stru...

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Problems solved by technology

[0004] However, since there is no shallow trench isolation structure formed between adjacent MOS transistors, there may be leakage current betw

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