Semiconductor device and its forming method, SRAM and its forming method

A static random, semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of low yield and poor performance of static random access memory, etc., and achieve the effect of high yield and good performance

Active Publication Date: 2017-12-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] refer to figure 2 , on figure 1 After the semiconductor device was cleaned, it was found that the above-mentioned cleaning solution also reacted with the isolation structure 102 located below the sidewall 110, resulting in the first dielectric layer 104 and the second dielectric layer 106 located below the metal gate 108 due to the interaction with the cleaning solution. reaction and be partially or completely removed, which will cause the formed NMOS transistor or PMOS transistor to fail, and the formed SRAM has poor performance and low yield

Method used

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  • Semiconductor device and its forming method, SRAM and its forming method
  • Semiconductor device and its forming method, SRAM and its forming method
  • Semiconductor device and its forming method, SRAM and its forming method

Examples

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no. 1 example

[0042] This embodiment describes the formation process of a semiconductor device.

[0043] refer to image 3 , providing a semiconductor substrate, the semiconductor substrate includes an active region 200 and two rows of isolation trenches 206 , the active region 200 is located between adjacent isolation trenches 206 .

[0044] Specifically, the material of the semiconductor substrate is silicon, silicon germanium or silicon-on-insulator. In this embodiment, the material of the semiconductor substrate is silicon.

[0045] In this embodiment, forming the semiconductor substrate including the active region 200 and two rows of isolation trenches 206 includes the following steps:

[0046] forming a mask layer 202a on the semiconductor substrate, and forming two rows of openings 204 in the mask layer 202a;

[0047] The semiconductor substrate is etched along the opening 204 to form two rows of isolation trenches 206 in the semiconductor substrate.

[0048] Wherein, the material ...

no. 2 example

[0082] refer to Figure 10 , is a top view of the SRAM formed in this embodiment, which includes the semiconductor device formed in the first embodiment.

[0083] The method for forming the SRAM provided by this embodiment, when forming Figure 9 After semiconductor devices, it also includes: Figure 9 The active region 200 on both sides of the middle gate structure is implanted with ions to form a source 222 and a drain 224 . The conductivity type of the source 222 and the drain 224 can be either N-type or P-type. The methods for forming the source 222 and the drain 224 are well known to those skilled in the art, and will not be described in detail here.

[0084] Correspondingly, refer to Figure 10 , this embodiment also provides a static random access memory, which includes Figure 9 In addition to the semiconductor device, it also includes a source 222 and a drain 224 .

[0085] The SRAM in this embodiment includes the semiconductor device in the first embodiment. Since...

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Abstract

A semiconductor device and its forming method and static random access memory and its forming method, the semiconductor device includes: a semiconductor substrate, the semiconductor substrate includes an active region and more than two rows of isolation trenches, the active region is located Between the adjacent isolation trenches; an isolation structure, the isolation structure includes a first isolation layer located on the bottom and sidewalls of the isolation trenches, a barrier layer located on the first isolation layer and located on the A second isolation layer on the barrier layer; a gate structure, the gate structure includes a first dielectric layer spanning the active region and at least part of the first isolation layer on both sides of the active region, located on the second A second dielectric layer on a dielectric layer and a metal gate on the second dielectric layer; side walls, the side walls are located on the isolation structure and cover the side walls of the gate structure, the side walls A wall covers at least part of the barrier layer. The semiconductor device formed by the invention has good performance and high yield.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and its forming method, a static random access memory and its forming method. Background technique [0002] With the continuous development of modern high-tech industries represented by electronic communication technology, the total output value of the world's integrated circuit industry is growing at a rate of 30% every year. Static random access memory is an important component in integrated circuits, with small size and high density. Among semiconductor memory devices, Static Random Access Memory (SRAM) has the advantages of lower power consumption and faster working speed compared with Dynamic Random Access Memory (DRAM). Therefore, SRAMs and methods of forming them are attracting more and more attention. [0003] SRAM cells can be classified into resistive load SRAM cells and CMOS SRAM cells. The resistive load SRAM cell uses a h...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L29/78H01L21/336H01L27/11H01L21/8244H10B10/00
CPCH01L29/0684H01L29/66477H01L29/78H10B10/12
Inventor隋运奇
OwnerSEMICON MFG INT (SHANGHAI) CORP