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Decoding of complex program instructions corresponding to multiple micro-ops

A technology of program instructions and complex programs, applied in the field of data processing, which can solve problems such as reduced processing performance

Inactive Publication Date: 2019-05-31
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This results in reduced processing performance

Method used

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  • Decoding of complex program instructions corresponding to multiple micro-ops
  • Decoding of complex program instructions corresponding to multiple micro-ops
  • Decoding of complex program instructions corresponding to multiple micro-ops

Examples

Experimental program
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Embodiment Construction

[0043] figure 1 A part of a data processing device 2 for processing data is schematically shown. The device 2 has processing circuitry 4 capable of executing multiple parallel processing threads. The device 2 executes an instruction set comprising complex program instructions corresponding to a plurality of micro-operations to be executed by the processing circuit 4 . Examples of complex program instructions are load multiple or store multiple instructions for loading multiple values ​​from memory to registers of processing circuit 4 or storing multiple values ​​from registers of processing circuit 4 to memory . A load multiple / store multiple instruction may be decoded to generate multiple micro-ops, each micro-op for loading / store of one of multiple values. Another example of complex program instructions are instructions for performing relatively complex arithmetic operations, such as square root operations or floating point arithmetic operations. Complex arithmetic opera...

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Abstract

The present invention relates to the decoding of complex program instructions corresponding to multiple micro-operations. The data processing device 2 has a processing circuit 4 capable of processing a plurality of parallel processing threads. Shared instruction decoder 30 decodes program instructions to generate micro-operations to be processed by processing circuit 4 . The instructions include at least one complex instruction having multiple micro-operations. A plurality of fetch units 8 are provided for fetching micro-operations generated by the decoder 30 for processing by the processing circuit 4 . Each acquisition unit 8 is associated with at least one of the threads. The decoder 30 individually generates a plurality of micro-operations of the complex instruction in response to separate decode requests 24 triggered by the fetch unit 8, each decode request 24 identifying which micro-operation of the complex instruction is to be responded to by the decoder 30 Decoding request 24 is generated.

Description

technical field [0001] The technology relates to the field of data processing. More particularly, the present technique relates to decoding program instructions to generate micro-operations in a data processing apparatus supporting parallel processing threads. Background technique [0002] Some instruction sets include complex program instructions corresponding to a plurality of micro-operations to be executed by the processing circuit, each micro-operation representing a portion of the operations associated with the program instruction. Accordingly, the instruction decoder may decode program instructions to generate micro-operations to be executed by the processing circuit. [0003] Some processing devices support multiple parallel processing threads. Separate fetch units may be provided for respective threads to trigger fetch micro-operations into the processing circuitry. A shared instruction decoder may be provided for generating the micro-ops required by the respecti...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/3017G06F9/3851G06F9/3887G06F9/30145G06F9/3888G06F9/262G06F8/41G06F9/3818G06F9/321G06F8/52
Inventor 鲁纳·霍姆
Owner ARM LTD
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