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A method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cache

A cache and cache line technology, applied in memory systems, register devices, machine execution devices, etc., can solve the problems of inefficient threading initiation/automatic generation, difficulty in automatic parallelization, and heavy weight

Active Publication Date: 2015-04-29
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, those threads are usually structured for coarse-grained parallelism, and incur heavy software overhead for initiation and synchronization, leaving fine-grained parallelism, such as function calls and loops executing in parallel, without efficient threading initiation / automatic generate
Such described overhead is accompanied by difficulties in automatic parallelization of non-explicit / easily parallelizable / threadable software code using state-of-the-art compiler or user parallelization techniques

Method used

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  • A method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cache
  • A method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cache
  • A method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cache

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Embodiment Construction

[0035] While this invention has been described in connection with one embodiment, it is not intended to be limited to the specific form set forth herein. On the contrary, it is intended to cover such alternatives, modifications and equivalents as may be properly included within the scope of the present invention as defined by the appended claims.

[0036] In the following detailed description, numerous specific details are set forth, such as specific method sequences, structures, elements, and connections. It is understood, however, that these and other specific details need not be utilized to practice embodiments of the invention. In other instances, well-known structures, elements or connections have been omitted or not described in particular detail to avoid unnecessarily obscuring the description.

[0037] Reference within this specification to "one embodiment" or "an embodiment" is intended to indicate that a particular feature, structure or characteristic described in c...

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Abstract

In a processor, a method for filtering stores to prevent all stores from having to snoop check against all words of a cache. The method includes implementing a cache wherein stores snoop the caches for address matches to maintain coherency; marking a portion of a cache line if a given core out of a plurality of cores loads from that portion by using an access mask; checking the access mask upon execution of subsequent stores to the cache line; and causing a miss prediction when a subsequent store to the portion of the cache line sees a prior mark from a load in the access mask.

Description

[0001] THIS APPLICATION REQUIRES THE CO-PENDING COMMON ASSIGNMENT TITLE "A METHOD AND SYSTEM FOR FILTERING THE STORES TO PREVENT ALL STORES FROM HAVING TO SNOOP CHECK AGAINST ALL WORDS OF A CACHE" FILLED JUNE 15, 2012 by Mohammad A. Abdallah The benefit of U.S. Provisional Patent Application Serial No. 61 / 660,553, which is hereby incorporated in its entirety. technical field [0002] The present invention relates generally to digital computer systems, and more particularly to systems and methods for selecting instructions, including sequences of instructions. Background technique [0003] Processors are required to handle multiple tasks that are either related or completely independent. The internal state of such processors usually consists of registers that may hold different values ​​at each particular moment of program execution. At each moment of program execution, the internal state image is called the architectural state of the processor. [0004] When architectural ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
CPCG06F12/0862G06F2212/6028G06F9/30047G06F9/3834G06F12/0831G06F9/30185G06F9/30145G06F9/3824G06F9/3851G06F9/30043G06F9/30098G06F2212/621
Inventor M·阿布达拉
Owner INTEL CORP