A virtual load store queue having a dynamic dispatch window with a distributed structure

Abstract

An out of order processor. The processor includes a distributed load queue and a distributed store queue that maintain single program sequential semantics while allowing an out of order dispatch of loads and stores across a plurality of cores and memory fragments; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load / store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.

Description

[0001] This application claims the benefit of co-pending commonly assigned U.S. Provisional Patent Application Serial No. 61 / 660,548, entitled "A VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A DISTRIBUTED STRUCTURE," filed June 15, 2012 by Mohammad A. Abdallah interest, and this application is incorporated herein in its entirety. technical field [0002] The present invention relates generally to digital computer systems, and more particularly to systems and methods for selecting instructions, including sequences of instructions. Background technique [0003] Processors are required to handle multiple tasks that are either related or completely independent. The internal state of such processors usually consists of registers that may hold different values ​​at each particular moment of program execution. At each moment of program execution, the internal state image is called the architectural state of the processor. [0004] When architectural code executi...

AI Technical Summary

Problems solved by technology

However, those threads are usually structured for coarse-grained parallelism, and incur heavy software overhead for initiation and synchronization, leaving fine-grained parallelism, such as function calls and loops executing in parallel, without efficient threading initiation / automatic generate

Such described overhead is accompanied by difficulties in automatic parallelization of non-explicit / easily parallelizable / threadable software code using state-of-the-art compiler or user parallelization techniques

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