Programmable high-speed differential interface

A high-speed differential and interface technology, used in instruments, electrical digital data processing, etc., can solve problems such as inability to meet multi-mode high-speed differential interface transmission, inability to expand, etc., to improve flexibility and scalability, and reduce manufacturing costs.

Active Publication Date: 2015-05-13
58TH RES INST OF CETC
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Problems solved by technology

[0003] The existing high-speed differential interfaces are all single-mode transmission signals, that is, they can only support LVDS transmission of DDR (Double Data Rate, double data rate) circuits, or ca

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  • Programmable high-speed differential interface

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[0027] The present invention will now be described in further detail with reference to the drawings. These drawings are all simplified schematic diagrams, which merely illustrate the basic structure of the present invention in a schematic manner, so they only show the structures related to the present invention.

[0028] Such as figure 1 As shown, a programmable high-speed differential interface includes input channel 1, output channel 2, and control module 3. Input channel 1 is used to receive external differential data and differential clock signals, and input parallel data and synchronous clock signals to the internal after conversion. Output channel 2 is used to receive internal parallel data and synchronous clock signals, and output differential data and differential clock signals after conversion. Externally, control module 3 controls input channel 1 to input data and output channel 2 to output data.

[0029] The input channel 1 includes a differential LVDS receiving module ...

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Abstract

The invention relates to a programmable high-speed differential interface. The programmable high-speed differential interface comprises an input channel, an output channel and a control module, wherein the input channel comprises a differential LVDS receiving module, an input clock adjustment module and a data inputting and boxing module, the an LVDS signal is converted into a single-end LVCMOS signal by the differential LVDS module and then is output, the data inputting and boxing module converts the single-end LVCMOS signal into parallel data and then inputs the parallel data to the interior, the output channel comprises a differential LVDS sending module, an output clock adjustment module and a data outputting and boxing module, the data outputting and boxing module converts the parallel data output from the interior into the single-end LVCMOS signal according to a complementary clock signal and then outputs the single-end LVCMOS signal, and the differential LVDS sending module converts the single-end LVCMOS signal into the LVDS signal, outputs the LVDS signal and outputs a differential clock signal at the same time. According to the programmable high-speed differential interface, the flexibility and the expansibility of a circuit can be improved, and manufacturing cost is reduced.

Description

technical field [0001] The invention belongs to the field of circuit high-speed interface, in particular to a programmable high-speed differential interface. Background technique [0002] In the field of high-speed interfaces, it is a common means to use differential signals to meet faster data output requirements. Sending a synchronous clock while transmitting data is a method to solve the signal synchronization at the receiving end, the most common is to send data once per clock cycle (SDR). With the increase of the transmission rate requirement, sending data (DDR) at the two edges of the clock at the same time has also become a development trend. [0003] The existing high-speed differential interfaces are all single-mode transmission signals, that is, they can only support LVDS transmission of DDR (Double Data Rate, double data rate) circuits, or can only support LVDS transmission of SDR (Single Data Rate, single data rate) circuits. ) circuit. It cannot meet the requ...

Claims

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Application Information

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IPC IPC(8): G06F13/40
Inventor 邹家轩魏敬和于宗光罗晟汤赛楠桂江华
Owner 58TH RES INST OF CETC
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