Clocking for Pipelined Routing

Abstract

An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers."

Description

[0001] This application claims priority to US Patent Application 14 / 075,802, filed November 8, 2013, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates to integrated circuits, and more particularly to pipelined interconnect circuits on integrated circuits and clocking / clocking of pipelined interconnect circuits. Background technique [0003] Each transition from one technology node to the next has resulted in smaller transistor sizes and thus potentially more functionality per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development due to reduced interconnect and cell delays, which has resulted in increased performance. However, recent technology nodes have observed a significant slowdown in latency reduction (ie, slowdown in performance improvement). [0004] To further improve performance, solutions such as register pipelining have been proposed, where addi...

AI Technical Summary

Problems solved by technology

However, performing register pipelining often involves a considerable amount of time and effort, as it is often necessary to iterate several times through the steps of locating performance bottlenecks, inserting and removing registers, and compiling the modified IC design

[0005] It is often the case that after many iterations of inserting and removing registers, register-pipelined IC designs still exhibit unsatisfactory performance because synchronous elements are placed far from each other and existing routing structure does not support high-speed connections across integrated circuits in an efficient manner

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