Packaging Structure and Method for Shrinking Dimensions of Semiconductor Devices

Abstract

The invention provides a structure and a method for packaging dimensionally shrunk semiconductor devices. The method for packaging the dimensionally shrunk semiconductor devices includes providing a semiconductor substrate for manufacturing a first product, manufacturing a second product on the semiconductor substrate; depositing a dielectric layer and forming a hole in the dielectric layer; forming a first bonding pad in the formed hole, forming second top metal layers on the surfaces of the first bonding pad and the dielectric layer, reserving the certain second top metal layer by a photoetching process; covering the certain second top metal layer and exposed surfaces of the dielectric layer with an insulating layer, and correspondingly manufacturing a second bonding pad in the insulating layer; aligning the second bonding pad by the aid of wafer-level packaging and testing processes for the first product and packaging and testing the structure. The second product is dimensionally shrunk according to the first product and is provided with a first top metal layer on the top of the second product. The certain second top metal layer is used for being connected to regions between the first bonding pad of the second product and the second bonding pad of the first product. The structure and the method have the advantages that the dimensionally shrunk products can be packaged by the aid of the original processes, accordingly, the packaging debugging time can be saved, and the product development cycle can be shortened.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging structure and method for shrinking the size of semiconductor devices. Background technique [0002] With the continuous advancement of semiconductor technology, the process nodes of the feature size are getting smaller and smaller, and the product performance is improving exponentially, but at the same time, the manufacturing cost is also basically rising exponentially. In the fierce market competition, practitioners are required not only to continuously innovate process nodes to keep up with the pace of the market, but also to fully tap the potential of existing processes to obtain products with better cost performance. Therefore, the industry often tries to shrink the size of a certain percentage (generally between 80% and 95%) on the basis of the original process, so that it can be achieved without or with little increase in cost. Incre...

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Problems solved by technology

However, if Figure 1b As shown, the WLP process is used to package the second product whose size is shrunk based on the original process. After the second product shrinks, the PAD on the WLP process cannot correspond to the shrunk second product one-to-one. The PAD position of the second product changes from the pattern PAD-2 set in the top metal layer of the second product, so the PAD on the WLP process cannot perform alignment packaging on the second product through the pattern PAD-2 on the second product

The usual practice in the industry is to re-adjust the entire WLP process for the contracted second product and conduct performance tests, which undoubtedly increases the instability in the performance test, wastes a lot of time, and prolongs the development cycle of new products

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