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Method and system for error correction code distribution in memory systems

A memory system and memory technology, applied in the field of error correction code distribution, can solve problems such as memory loss and adverse performance impact

Active Publication Date: 2018-09-18
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this will result in a memory loss of the overall system memory and will adversely affect performance

Method used

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  • Method and system for error correction code distribution in memory systems
  • Method and system for error correction code distribution in memory systems
  • Method and system for error correction code distribution in memory systems

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Experimental program
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Embodiment Construction

[0018] In an embodiment, each memory device (eg, dynamic random access memory or DRAM) in a group of memory devices on the memory bus includes a local error correction code (ECC) computed based on the data block and memory device. As one example, nine memory devices each have a device data bus width of 8 bits and support a burst length of 8. Thus, each burst write to a memory device includes up to 513 bits of data and 63 bits of local ECC, which can be allocated as 57 bits of data and 7 bits of local ECC per memory device. Assigning local ECC bits to each memory device can support multiple errors in each memory device, such as one or two bit flips. Additional failure mode coverage can be achieved by adding a global ECC storage memory device to store the global ECC computed across all banked devices in addition to the local ECC values ​​for each device. Global ECC can correct for failures of the entire memory device or single / double bit failures in a single memory device. Glo...

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PUM

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Abstract

According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to divide write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and combine each data block with the corresponding local ECC instance for each memory The device forms encoded data blocks. Furthermore, the memory controller is configured to write each encoded data block to the memory device such that each memory device stores one of the data blocks with a corresponding instance of the local ECC . The memory system may further include a global ECC and a local ECC of the global ECC.

Description

technical field [0001] The present disclosure relates generally to computer memory, and more particularly to error correction code distribution in memory systems. Background technique [0002] Computer systems often require a considerable amount of high-speed random access memory (RAM) to temporarily hold information such as data and programs when starting up and operating. This information is normally binary, consisting of patterns of ones and zeros called data bits. The data bits are often grouped and organized at a higher level. For example, bytes often consist of eight bits; more generally, these groups or bytes are called symbols and can consist of any number of bits or sub-symbols. [0003] The density of memory devices continues to increase as computer systems become more powerful. In some cases, the RAM contents of a single computer can consist of hundreds of trillions of bits. Unfortunately, just a portion of a single RAM device can cause system-wide problems. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42
CPCG06F2211/109G06F11/108G06F11/1012G06F11/1008
Inventor P·W·科图斯H·C·亨特C·A·基尔默金圭贤W·E·莫尔K·L·赖特
Owner GLOBALFOUNDRIES INC