Method and system for error correction code distribution in memory systems
A memory system and memory technology, applied in the field of error correction code distribution, can solve problems such as memory loss and adverse performance impact
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[0018] In an embodiment, each memory device (eg, dynamic random access memory or DRAM) in a group of memory devices on the memory bus includes a local error correction code (ECC) computed based on the data block and memory device. As one example, nine memory devices each have a device data bus width of 8 bits and support a burst length of 8. Thus, each burst write to a memory device includes up to 513 bits of data and 63 bits of local ECC, which can be allocated as 57 bits of data and 7 bits of local ECC per memory device. Assigning local ECC bits to each memory device can support multiple errors in each memory device, such as one or two bit flips. Additional failure mode coverage can be achieved by adding a global ECC storage memory device to store the global ECC computed across all banked devices in addition to the local ECC values for each device. Global ECC can correct for failures of the entire memory device or single / double bit failures in a single memory device. Glo...
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