Novel test control circuit capable of improving chip robustness and novel test control method capable of improving chip robustness
A technology for testing circuits and control circuits, which is applied in the field of information security and can solve problems such as chip data rewriting
Active Publication Date: 2015-06-03
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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Problems solved by technology
If the chip is subjected to external interference during use and the DFF1Q terminal jumps, the chip will enter the test mode, and unexpected actions will occur, which may cause the data in the chip to be rewritten
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Embodiment Construction
[0012] The specific implementation manner of the present invention will be described below by taking a test circuit triggered by a rising edge as an example.
[0013] Such as figure 2 As shown, the test enable signal (signal 1) is connected to the Q terminal of the register DFF2 through the fuse line placed in the scribe slot, the D terminal of DFF2 is connected to a high level, and the DFF2 set terminal is connected to the power-on reset signal (signal 2 ), the signal 1 remains at a high level during the power-on reset process, and after the power-on reset is completed, the signal 1 is driven to a high level by the DFF2Q terminal, and the test enable is valid. When the fuse line is cut, the signal 1 is disconnected from the DFF2Q terminal, and the low level is maintained through the pull-down resistor, the test enable is invalid, and the chip exits the test mode.
[0014] Signal 1 and signal 2 pass through AND gate AND1 to generate a reset signal (signal 3) for resetting DF...
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The invention discloses a novel test control circuit capable of improving the chip robustness and a novel test control method capable of improving the chip robustness and provides a novel test control circuit capable of preventing a chip from abnormally entering a test mode during normal application and thus causing abnormal rewriting of data in the chip. The circuit is capable of controlling a clock signal and a resetting signal of a test circuit by virtue of test enable signals; after the test enable signals are invalid, the clock signal of the test circuit is closed, meanwhile the resetting signal of the test circuit is kept in a low level, and therefore the test circuit cannot be started, so that the possibility that the chip abnormally enters the test mode is greatly reduced, the possibility of abnormally entering the test mode to cause rewriting of the data in the chip is reduced, and the chip robustness is improved. The novel test control circuit and the novel test control method have favorable innovativeness, practicability and validity.
Description
technical field [0001] The invention is mainly applied in the technical field of information security, and improves the robustness of the chip without reducing the security. Background technique [0002] In the design of the chip, the test mode often has the maximum read and write control authority. In order to protect the security of user data stored in the chip, the test state must be exited after the chip test is completed, but the chip is used due to external interference during the use of the chip. The test control circuit starts to make the chip enter the test state, and there is a risk that the data in the chip will be rewritten unexpectedly. The schematic diagram of the usual test control circuit design is as follows: figure 1 As shown, put the test enable signal into the dicing groove of the wafer. The test enabling signal is valid during the wafer test, and the chip is in the test state. After the test is completed, the fuse placed in the dicing groove is broken. ...
Claims
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IPC IPC(8): G01R31/28
Inventor 范长永周永存
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD