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A multi-core DMA segmented data transfer method using host counting for gpdsp

A segmented data and transmission method technology, applied in electrical digital data processing, instruments, etc., can solve problems such as small bit width, insufficient calculation accuracy and addressing space, and limit data transmission efficiency, so as to reduce load and lighten the on-chip network Load, effective perception of the effect of memory access characteristics

Active Publication Date: 2017-12-12
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0004] General scientific computing requires high-performance DSP, but traditional DSP has the following disadvantages when used in scientific computing: 1) The bit width is small, which makes the calculation accuracy and addressing space insufficient
The data exchange of multi-core chips needs to be transmitted through the on-chip network. Excessively high on-chip network load will limit the data transmission efficiency. Efficient multi-core DMA design must reduce the load on the on-chip network

Method used

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  • A multi-core DMA segmented data transfer method using host counting for gpdsp
  • A multi-core DMA segmented data transfer method using host counting for gpdsp
  • A multi-core DMA segmented data transfer method using host counting for gpdsp

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Embodiment Construction

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0039] Such as figure 1 Shown is a schematic diagram of the GPDSP architecture of the method of the present invention in a specific application example. The multi-core GPDSP processor is composed of DSP nodes, on-chip network and DDR3SDRAM outside the core. Each DSP node includes a DSP core, and the network-on-chip implements data communication between each DSP node and between the DSP node and an external storage unit. Such as figure 2 Shown is a schematic diagram of the location of the DMA in the GPDSP calculation kernel in this embodiment. DMA is connected with components such as peripheral hardware configuration bus (PBUS), vector memory (Vector Memory, VM) and scalar memory (Scalar Memory, SM) in the DSP core. Among them, the scalar processing unit SPU configures transmission parameters for the DMA unit through the periphera...

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Abstract

A kind of multi-core DMA segmentation data transmission method that adopts host computer counting for GPDSP, its transmission process is: host DMA starts, generates segmentation data transmission request according to configuration parameter; Carrying the return data selection vector of the returned data target node, each bit of the returned data selection vector indicates whether the corresponding core is the target node for reading the returned data; when the data corresponding to the read request is returned, the network-on-chip will select the vector according to the returned data The data is distributed to the corresponding DMA; the host DMA counts the transmitted data; when the count is completed, the host DMA sends a signal to clear the receive buffer to all the slave DMAs involved in the transmission transaction; when all the slave DMA clears the receive buffer, the data transmission Transaction complete. The invention has the advantages of simple principle, convenient operation, flexible configuration, high memory access efficiency and the like.

Description

technical field [0001] The present invention mainly relates to the field of General Purpose Digital Signal Processor (GPDSP), in particular to a DMA segmented data transmission method using host counting. Background technique [0002] Digital signal processor (Digital Signal Processor, DSP) as a typical embedded microprocessor is widely used in embedded systems. , has brought great opportunities to the development of signal processing, and its application fields have expanded to all aspects of military and economic development. In the application fields of modern communication, image processing and radar signal processing, as the amount of data processing increases, the requirements for calculation accuracy and real-time performance increase, and it is usually necessary to use a higher-performance microprocessor for processing. [0003] Different from the central processing unit CPU, DSP has the following characteristics: 1) Strong computing power, focusing on real-time com...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/32
Inventor 马胜杨柳陈书明万江华郭阳刘宗林孙书为刘仲雷元武刘胜王耀华王占立田玉恒胡月安丁一博
Owner NAT UNIV OF DEFENSE TECH
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