Chip package structure

Abstract

A chip packaging structure includes a chip. A plurality of first pads and a plurality of second pads are arranged on two sides of the chip respectively. The plurality of first pads are electrically connected to a chip select electrode, the plurality of second pads and the exposed conductor correspondingly. The first pads and the second pads electrically connected to each other are not aligned in the vertical direction, and are connected by vertical connectors and inner conductors. The chip includes a plurality of insulating layers, and the inner conductors are separated at different heights by the plurality of insulating layers.

Description

technical field [0001] The invention relates to a chip package comprising at least one stackable chip. Background technique [0002] Chip stacking technology allows two chips to be closer together, thereby enabling faster data transmission between the two chips and consuming less energy. Memory chips can be stacked together to obtain a memory module with larger storage space. In addition to stacking the same two chips, chips with different functions can also be stacked together to combine different functions. [0003] In a memory chip stack, each memory chip has a chip select (CS) terminal. The chip select electrode is used to activate the memory chip. For example, a DRAM chip may have a row address strobe (RAS), a row address strobe (column address strobe) or a chip select pin as a chip select electrode. When a signal is applied to the chip-select electrodes of a chip in the stack of memory chips, that chip can be accessed while other chips cannot. [0004] Traditional...

AI Technical Summary

Problems solved by technology

These wires need additional process to form, so it will increase the production cost

In addition, long wires cause signal delay and take up more space, resulting in a large stack of memory chips

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